Patents by Inventor Michael Lane

Michael Lane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Kickover Tool and Selective Mandrel System
    Publication number: 20070267200
    Abstract: A kickover tool is disclosed for installing and retrieving a well flow control device from a side pocket mandrel in a wellbore. The kickover tool includes a spring-loaded key which has an outer circumferential surface having a predetermined machined pattern formed therein. Each side pocket mandrel in the tubing string contains a profile having a predetermined machined pattern. The spring-loaded key will engage the side pocket mandrel with a profile matching the pattern on the outer circumferential surface of the spring-loaded key. When that engagement occurs, the articulated arm of the kickover tool is permitted to be deployed to insert a well flow control device in the side pocket of the side pocket mandrel.
    Type: Application
    Filed: May 18, 2006
    Publication date: November 22, 2007
    Applicant: SCHLUMBERGER TECHNOLOGY CORPORATION
    Inventors: Elijah Jackson, Michael Lane, Tyson Messick, Kenneth Burnett
  • UV feature illumination
    Patent number: 7261481
    Abstract: In an aspect of the present invention, methods and systems for providing an input device are disclosed. In an aspect of the present invention, the input device includes a symbol and a UV light source is provided to direct UV light on the symbol. The symbol includes an UV excitable compound. In an aspect of the invention, the UV light from the UV light source is directed onto the symbol with a light pipe. In operation, the UV light causes the symbol to glow so that the symbol is visible in a darkened environment.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: August 28, 2007
    Assignee: Microsoft Corp.
    Inventors: David Michael Lane, Thomas Patrick Lennon
  • Container having segmented bumper rib
    Publication number: 20070170144
    Abstract: A plastic container has an upper portion including a mouth defining an opening into the container. A shoulder region extends from the upper portion. A sidewall portion extends from the shoulder region to a base portion. The base portion closes off an end of the container. An upper bumper portion is defined at a transition between the shoulder region and the sidewall portion. The upper bumper portion includes an upper raised wall defining a maximum width of the container. The upper raised wall includes a recessed portion formed therein. A lower bumper portion is defined at a transition between the base portion and the sidewall portion. The lower bumper portion includes a lower raised wall defining the maximum width of the container. The lower raised wall includes a recessed portion formed therein.
    Type: Application
    Filed: January 25, 2006
    Publication date: July 26, 2007
    Inventors: Michael Lane, Mark Blystone, G. Lisch, Richard Rangler
  • Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer
    Publication number: 20070148958
    Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
    Type: Application
    Filed: August 4, 2006
    Publication date: June 28, 2007
    Inventors: Lawrence Clevenger, Stefanie Chiras, Timothy Dalton, James Demarest, Derren Dunn, Chester Dziobkowski, Philip Flaitz, Michael Lane, James Lloyd, Darryl Restaino, Thomas Shaw, Yun-Yu Wang, Chih-Chao Yang
  • ALIGNMENT MARK WITH IMPROVED RESISTANCE TO DICING INDUCED CRACKING AND DELAMINATION IN THE SCRIBE REGION
    Publication number: 20070108638
    Abstract: A robust alignment mark used in semiconductor processing to help deter the expansion of cracks and delamination caused by the cutting of a dicing blade. A cross-shaped structure is used as a line site for alignment of the dicing blade. A plurality of rectangular elements is situated about the periphery of the alignment mark and populated with via bar structures that are interconnected at each level of the wafer, and laid in a serpentine fashion throughout each element to expose more of the via bar structure surface area to propagating cracks. The rectangular elements are formed of different sizes to expose more surface area to propagating cracks. A plurality of square, metal-level structures is formed in the area between the cross-shaped structure and the peripherally placed, rectangular elements.
    Type: Application
    Filed: November 16, 2005
    Publication date: May 17, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael Lane, Christopher Muzzy, Roger Yerdon
  • Rectangular hot-filled container
    Publication number: 20070039918
    Abstract: A rectangular plastic container having a shoulder region adapted for vacuum pressure absorption, a sidewall portion having a rigid support ledge and a tapered base structure having an octagonal shaped footprint. The shoulder region including vacuum panels being moveable to accommodate vacuum related forces generated within the container. The shoulder region, sidewall portion and base each having differing horizontal cross sectional shapes.
    Type: Application
    Filed: August 22, 2005
    Publication date: February 22, 2007
    Inventors: Michael Lane, Dan Weissmann, John Nievierowski, Brad Caszatt
  • Line level air gaps
    Publication number: 20060264036
    Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.
    Type: Application
    Filed: July 24, 2006
    Publication date: November 23, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shyng-Tsong Chen, Stefanie Chiras, Matthew Colburn, Tomothy Dalton, Jeffrey Hedrick, Elbert Huang, Kaushik Kumar, Michael Lane, Kelly Malone, Chandrasekhar Narayan, Satyanarayana Nitta, Sampath Purushothaman, Robert Rosenberg, Christy Tyberg, Roy Yu
  • Apparatus and method for controlling operation of a processor device during startup
    Patent number: 7116139
    Abstract: An apparatus for controlling operation of a processor device during startup of the processor device includes: (a) a signal treating circuit receiving a voltage supply signal at a voltage supply locus; the signal treating circuit using the voltage supply signal for generating a first treated signal and a second treated signal; and (b) an output circuit coupled with the signal treating circuit; the output circuit receiving the first treated signal and the second treated signal and generating a control signal at an output locus based upon a relationship between the first treated signal and the second treated signal; the output locus being coupled with the processor device; the control signal effecting the controlling.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: October 3, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Michael Lane Mitchell
  • Circumferential stiffening rib for hot-fill containers
    Publication number: 20060186083
    Abstract: A polymer container suitable for hot-filling featuring at least one circumferential rib having a plurality of varying width regions transitioning from a smaller dimension area, to a larger dimension area, to the smaller dimension area. The larger dimension area is adjacent a land area between any two adjacent vacuum panels.
    Type: Application
    Filed: February 24, 2005
    Publication date: August 24, 2006
    Inventors: Rohit Joshi, Michael Lane, Richard Steih
  • Hot-fillable blow molded container with pinch-grip vacuum panels
    Publication number: 20060180568
    Abstract: A polymer container suitable for hot-filling featuring a pinch-grip vacuum panel combination having a flexible-field and a generally ridged pinch-grip that accommodates vacuum related forces.
    Type: Application
    Filed: February 14, 2005
    Publication date: August 17, 2006
    Inventor: Michael Lane
  • SiCOH dielectric material with improved toughness and improved Si-C bonding, semiconductor device containing the same, and method to make the same
    Publication number: 20060165891
    Abstract: A low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided that includes atoms of Si, C, O, and H in which a fraction of the C atoms are bonded as Si—CH3 functional groups, and another fraction of the C atoms are bonded as Si—R—Si, wherein R is phenyl, —[CH2]n— where n is greater than or equal to 1, HC?CH, C?CH2, C?C or a [S]n linkage, where n is a defined above.
    Type: Application
    Filed: May 18, 2005
    Publication date: July 27, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel Edelstein, Stephen Gates, Alfred Grill, Michael Lane, Qinghuang Lin, Robert Miller, Deborah Neumayer, Son Nguyen
  • Metal capped copper interconnect
    Publication number: 20060157857
    Abstract: A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 atomic percent or greater of the one or more metals. The invention is also directed to a method of making a conducting material comprising: providing an underlayer; contacting the underlayer with a seed layer, the seed layer comprising copper and one or more metals selected from iridium, osmium and rhenium; depositing a conducting layer comprising copper on the seed layer, and annealing the conducting layer at a temperature sufficient to cause grain growth in the conducting layer, yet minimize the migration of the one or more alloy metals from the seed layer to the conducting layer.
    Type: Application
    Filed: March 16, 2006
    Publication date: July 20, 2006
    Applicant: International Business Machines Corporation
    Inventors: Michael Lane, Stefanie Chiras, Terry Spooner, Robert Rosenberg
  • Hardmask for improved reliability of silicon based dielectrics
    Publication number: 20060091559
    Abstract: The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.
    Type: Application
    Filed: November 4, 2004
    Publication date: May 4, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Son Nguyen, Michael Lane, Stephen Gates, Xiao Liu, Vincent McGahay, Sanjay Mehta, Thomas Shaw
  • Silicon chip carrier with conductive through-vias and method for fabricating same
    Publication number: 20060027934
    Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.
    Type: Application
    Filed: October 3, 2005
    Publication date: February 9, 2006
    Inventors: Daniel Edelstein, Paul Andry, Leena Buchwalter, Jon Casey, Sherif Goma, Raymond Horton, Gareth Hougham, Michael Lane, Xiao Liu, Chirag Patel, Edmund Sprogis, Michelle Steen, Brian Sundlof, Cornelia Tsang, George Walker, Yu-Ting Cheng, Kenneth Ocheltree, Robert Montoye
  • INTERLEVEL DIELECTRIC LAYER AND METAL LAYER SEALING
    Publication number: 20060024961
    Abstract: Methods for sealing an organic ILD layer and a metal layer after an etching step. The method includes etching through an ILD layer and leaving a remaining portion of an underlying metal layer cap, maintaining the device in an inert gas, and depositing at least a portion of a liner into the opening to seal the ILD layer and the metal layer. Subsequent processing may include formation of a via by etching through the portion of the liner and the remaining portion of the cap layer, and depositing a metal.
    Type: Application
    Filed: July 29, 2004
    Publication date: February 2, 2006
    Inventors: Matthew Angyal, Peter Biolsi, Lawrence Clevenger, Habib Hichri, Bernd Kastenmeier, Michael Lane, Jeffrey Marino, Vincent McGahay, Theodorus Standaert
  • Stacked via-stud with improved reliability in copper metallurgy
    Publication number: 20060014376
    Abstract: A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material.
    Type: Application
    Filed: September 20, 2005
    Publication date: January 19, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Birendra Agarwala, Conrad Barile, Hormazdyar Dalal, Brett Engel, Michael Lane, Ernest Levine, Xiao Liu, Vincent McGahay, John McGrath, Conal Murray, Jawahar Nayak, Du Nguyen, Hazara Rathore, Thomas Shaw
  • Reliability of low-k dielectric devices with energy dissipative layer
    Publication number: 20060012014
    Abstract: The present invention provides a plastically and/or viscoelastically deformable layer that can be used in conjunction with a low-k dielectric (k of less than 4.0) to provide an electronic semiconductor structure having improved reliability. The deformable layer can be incorporated into various points within an electronic structure to dissipate energy within the structure that may cause the low-k dielectric material to crack or delaminate therefrom. Moreover, the presence of the deformable layer with the electronic structure improves the overall strength of the resultant structure.
    Type: Application
    Filed: July 15, 2004
    Publication date: January 19, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shyng-Tsong Chen, Stefanie Chiras, Michael Lane, Qinghuang Lin, Robert Rosenberg, Thomas Shaw, Terry Spooner
  • Copper conductor
    Publication number: 20060006070
    Abstract: A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 atomic percent or greater of the one or more metals. The invention is also directed to a method of making a conducting material comprising: providing an underlayer; contacting the underlayer with a seed layer, the seed layer comprising copper and one or more metals selected from iridium, osmium and rhenium; depositing a conducting layer comprising copper on the seed layer, and annealing the conducting layer at a temperature sufficient to cause grain growth in the conducting layer, yet minimize the migration of the one or more alloy metals from the seed layer to the conducting layer.
    Type: Application
    Filed: July 9, 2004
    Publication date: January 12, 2006
    Applicant: International Business Machines Corporation
    Inventors: Michael Lane, Stefanie Chiras, Terry Spooner, Robert Rosenberg, Daniel Edelstein
  • Method for electroplating on resistive substrates
    Patent number: 6974531
    Abstract: A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: December 13, 2005
    Assignee: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Hariklia Deligianni, Wilma Jean Horkans, Keith T. Kwietniak, Michael Lane, Sandra G. Malhotra, Fenton Read McFeely, Conal Murray, Kenneth P. Rodbell, Philippe M. Vereecken
  • Stacked via-stud with improved reliability in copper metallurgy
    Patent number: 6972209
    Abstract: A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: December 6, 2005
    Assignee: International Business Machines Corporation
    Inventors: Birendra N. Agarwala, Conrad A. Barile, Hormazdyar M. Dalal, Brett H. Engle, Michael Lane, Ernest Levine, Xiao Hu Liu, Vincent McGahay, John F. McGrath, Conal E. Murray, Jawahar P. Nayak, Du B. Nguyen, Hazara S. Rathore, Thomas M. Shaw