Abstract: An improved integrated Clos network may include a plurality of servers, each server comprising a processor and a network interface chip, and a plurality of cross bar switches, each cross bar switch having a direct connection to each network interface chip such that a data packet can be transferred between any two servers by means of any cross bar switch. Each network interface chip can be configured to receive a data packet directly from memory associated with the processor comprising the same server as the network interface chip, read and process the data packet in order to produce a processed data packet configured to be routed from the network interface chip via a cross bar switch to a network interface chip associated with a different server, select a cross bar switch, and transmit the processed data packet to the selected cross bar switch.

Abstract: A packet switching system for a packet transfer network, the system having an architecture including a plurality of line cards, each including an ingress path pipeline, with processing elements, and an egress buffer, and an electro-optical In/Out (IO) interconnect coupling the line cards to one another in a full mesh connectivity, in the absence of a switch fabric, wherein the ingress path pipeline of each line card is coupled by means of the electro-optical IO interconnect to the egress buffer of each of the plurality of line cards.

Abstract: The present disclosure allows connection between optical and electrical devices at high frequencies and high bit rate. The present disclosure provides an electro-optical device that includes an optical interface for optical signal transmission and reception; an electrical interface for electrical signal transmission and reception; a data and signal unit located inside an integrated circuit chip coupled to the optical interface and to the electrical interface for manipulating data received through said interfaces; and a processing unit located inside the integrated circuit chip coupled to the optical interface and to the electrical interface for processing digital data received through said interfaces. The present disclosure provides devices that achieve smaller physical dimensions with an increased number of interfaces to allow greater throughput of data into and out of the integrated circuit.

Abstract: The present disclosure allows connection between optical and electrical devices at high frequencies and high bit rate. The present disclosure provides an electro-optical device that includes an optical interface for optical signal transmission and reception; an electrical interface for electrical signal transmission and reception; a data and signal unit located inside an integrated circuit chip coupled to the optical interface and to the electrical interface for manipulating data received through said interfaces; and a processing unit located inside the integrated circuit chip coupled to the optical interface and to the electrical interface for processing digital data received through said interfaces. The present disclosure provides devices that achieve smaller physical dimensions with an increased number of interfaces to allow greater throughput of data into and out of the integrated circuit.

Abstract: A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network is disclosed. The linecard has two paths: a receive path and a transmit path. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information. Each packet is buffered and enqueued for transmission over the switching fabric to a destination linecard. The transmit path includes a buffer/queuing circuit similar to that used in the receive path. Both enqueuing and dequeuing of packets is accomplished using a CoS-based decision making apparatus.

Abstract: A matrix processor and processing method, the processor including a data encoder for receiving an input data stream; a data controller coupled to the data encoder for arranging the input data in an operand matrix, at least one processing unit for processing the data in matrix form by Boolean matrix-matrix multiplication with a selected operator matrix, and an output control module coupled to the processing unit for outputting desired results therefrom.

Abstract: A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network is disclosed. The linecard has two paths: a receive path and a transmit path. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information. Each packet is buffered and enqueued for transmission over the switching fabric to a destination linecard. The transmit path includes a buffer/queuing circuit similar to that used in the receive path. Both enqueuing and dequeuing of packets is accomplished using a CoS-based decision making apparatus.

Abstract: A bit-matrix processor including a pair of optoelectronic matrices and a controller for causing the matrices to perform Boolean Matrix transforms to perform logical operations, wherein Boolean logical equivalents include logical AND to replace element-wise multiplication, and logical OR instead of summation. According to one embodiment, the processor includes an optical source matrix for receiving input binary data; a passive optical replicator for replicating a pattern on the optical source matrix and projecting it onto a Spatial Light Modulator (SLM); a database loading device for loading data onto the SLM thereby to perform logical AND with the optical source matrix data; an integrating device for integrating light from the SLM onto a photodiode matrix; and an output signal processing device.

Abstract: A packet switching system for a packet transfer network, the system having an architecture including a plurality of line cards, each including an ingress path pipeline, with processing elements, and an egress buffer, and an electro-optical In/Out (IO) interconnect coupling the line cards to one another in a full mesh connectivity, in the absence of a switch fabric, wherein the ingress path pipeline of each line card is coupled by means of the electro-optical IO interconnect to the egress buffer of each of the plurality of line cards.

Abstract: A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port.

Abstract: A hierarchical traffic management system and method (i.e., a QoS behavioral model) are disclosed herein. The system includes a classifier operable to identify and classify incoming traffic streams and a queuing system. The queuing system includes a plurality of queues and is operable to apply scheduling policies to the traffic streams. The queues of the queuing system each include enqueue attributes configured to control a depth of the queue and dequeue attributes configured to control scheduling of the queue. The dequeue attributes include minimum bandwidth, maximum bandwidth, excess bandwidth, and priority, wherein each of the queues has one or more of the dequeue attributes defined.

Abstract: A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in a multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Using bandwidth management techniques, each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port.

Abstract: A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port.

Abstract: Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to individual packet processors and gathering the processed packet or subsets and forwarding the resultant modified or otherwise processed packets, accessing packet processing resources across a shared resource network, accessing packet processing resources using direct memory access techniques, and/or storing one overlapping portion of a packet in a global packet memory while providing a second overlapping portion to a packet processor. In one implementation, a packet of multiple streams of packets is received. A subset of bytes of the packet are distributed to the next packet processor determined based on a distribution pattern. The subset of the packet is processed to generate a modified subset, which is gathered in turn based on the distribution pattern; and a modified packet including the modified subset is forwarded.

Abstract: The invention provides a method and system for operating a switch, in which incoming data cells are converted from parallel to serial for synchronous input to a switch interconnect, converted from serial to parallel for parallel switching, converted from parallel to serial for synchronous output from the switch interconnect, and converted from serial to parallel for output. The switch interconnect and its input and output interfaces are controlled by a single frequency source, so that all serial data communication paths into and out of the switch interconnect are phase synchronized to within one clock cycle. A single frequency source for the switch system is coupled to the input interfaces, to output interfaces, and to the switch interconnect. The input interfaces each include a PLL which synchronizes to the single frequency source once for all serial communication to the switch interconnect.

Abstract: A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port.

Abstract: A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in a multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Using bandwidth management techniques, each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port.

Abstract: A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in a multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Using bandwidth management techniques, each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port.

Abstract: A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port.

Abstract: A hierarchical traffic management system and method (i.e., a QoS behavioral model) are disclosed herein. The system includes a classifier operable to identify and classify incoming traffic streams and a queuing system. The queuing system includes a plurality of queues and is operable to apply scheduling policies to the traffic streams. The queues of the queuing system each include enqueue attributes configured to control a depth of the queue and dequeue attributes configured to control scheduling of the queue. The dequeue attributes include minimum bandwidth, maximum bandwidth, excess bandwidth, and priority, wherein each of the queues has one or more of the dequeue attributes defined.