Abstract: A light emitting device includes an LED having a (e.g., top) light output surface, a ceramic phosphor, and an adhesive layer positioned to attach the top of the LED to the ceramic phosphor. In one embodiment the adhesive layer is composed of multiple separate patches (regions) that define at least one channel therebetween, with the channel being open to an environment to permit oxygen permeation. The adhesive layer can be applied by a patternable dispensing system.

Abstract: Devices and techniques are disclosed herein which include a first LED device layer, a second LED device layer, and an adhesive bondline disposed between the first LED device layer and the second LED device layer. The adhesive bondline includes a bondline thickness, a plurality of spacers disposed within the adhesive bondline, and a silicone matrix. The plurality of spacers may have a diameter or a shortest axis between 0.5 and 10 micrometers and the coefficient of variation is 10% or less. The plurality of spacers may be include SiO2, alumina, soda lime glass, may be inorganic, or polymeric.

Abstract: Devices and techniques are disclosed herein which include a first LED device layer, a second LED device layer, and an adhesive bondline disposed between the first LED device layer and the second LED device layer. The adhesive bondline includes a bondline thickness, a plurality of spacers disposed within the adhesive bondline, and a silicone matrix. The plurality of spacers may have a diameter or a shortest axis between 0.5 and 10 micrometers and the coefficient of variation is 10% or less. The plurality of spacers may be include SiO2, alumina, soda lime glass, may be inorganic, or polymeric.

Abstract: A light emitting device includes an LED having a (e.g., top) light output surface, a ceramic phosphor, and an adhesive layer positioned to attach the top of the LED to the ceramic phosphor. In one embodiment the adhesive layer is composed of multiple separate patches (regions) that define at least one channel therebetween, with the channel being open to an environment to permit oxygen permeation. The adhesive layer can be applied by a patternable dispensing system.

Abstract: Devices and techniques are disclosed herein which include a first LED device layer, a second LED device layer, and an adhesive bondline disposed between the first LED device layer and the second LED device layer. The adhesive bondline includes a bondline thickness, a plurality of spacers disposed within the adhesive bondline, and a silicone matrix. The plurality of spacers may have a diameter or a shortest axis between 0.5 and 10 micrometers and the coefficient of variation is 10% or less. The plurality of spacers may be include SiO2, alumina, soda lime glass, may be inorganic, or polymeric.

Abstract: Devices and techniques are disclosed herein which include a first LED device layer, a second LED device layer, and an adhesive bondline disposed between the first LED device layer and the second LED device layer. The adhesive bondline includes a bondline thickness, a plurality of spacers disposed within the adhesive bondline, and a silicone matrix. The plurality of spacers may have a diameter or a shortest axis between 0.5 and 10 micrometers and the coefficient of variation is 10% or less. The plurality of spacers may be include SiO2, alumina, soda lime glass, may be inorganic, or polymeric.

Abstract: Methods of forming silicon carbide power devices are provided. An n? silicon carbide layer is provided on a silicon carbide substrate. A p-type silicon carbide well region is provided on the n? silicon carbide layer. A buried region of p+ silicon carbide is provided on the p-type silicon carbide well region. An n+ region of silicon carbide is provided on the buried region of p+ silicon carbide. A channel region of the power device is adjacent the buried region of p+ silicon carbide and the n+ region of silicon carbide. An n? region is provided on the channel region and a portion of the n? region is removed from the channel region so that a portion of the n? region remains on the channel region to provide a reduction in a surface roughness of the channel region.

Abstract: Methods of forming silicon carbide power devices are provided. An n? silicon carbide layer is provided on a silicon carbide substrate. A p-type silicon carbide well region is provided on the n? silicon carbide layer. A buried region of p+ silicon carbide is provided on the p-type silicon carbide well region. An n+ region of silicon carbide is provided on the buried region of p+ silicon carbide. A channel region of the power device is adjacent the buried region of p+ silicon carbide and the n+ region of silicon carbide. An n? region is provided on the channel region and a portion of the n? region is removed from the channel region so that a portion of the n? region remains on the channel region to provide a reduction in a surface roughness of the channel region.

Abstract: Methods of forming silicon carbide power devices are provided. An n? silicon carbide layer is provided on a silicon carbide substrate. A p-type silicon carbide well region is provided on the n? silicon carbide layer. A buried region of p+ silicon carbide is provided on the p-type silicon carbide well region. An n+ region of silicon carbide is provided on the buried region of p+ silicon carbide. A channel region of the power device is adjacent the buried region of p+ silicon carbide and the n+ region of silicon carbide. An n? region is provided on the channel region and a portion of the n? region is removed from the channel region so that a portion of the n? region remains on the channel region to provide a reduction in a surface roughness of the channel region.

Abstract: Methods of forming silicon carbide power devices are provided. An n? silicon carbide layer is provided on a silicon carbide substrate. A p-type silicon carbide well region is provided on the n? silicon carbide layer. A buried region of p+ silicon carbide is provided on the p-type silicon carbide well region. An n+ region of silicon carbide is provided on the buried region of p+ silicon carbide. A channel region of the power device is adjacent the buried region of p+ silicon carbide and the n+ region of silicon carbide. An n? region is provided on the channel region and a portion of the n? region is removed from the channel region so that a portion of the n? region remains on the channel region to provide a reduction in a surface roughness of the channel region.

Abstract: Power devices are provided including a p-type conductivity well region and a buried p+ conductivity region in the p-type conductivity well region. An n+ conductivity region is provided on the buried p+ conductivity region. A channel region of the power device is provided adjacent the buried p+ conductivity region and n+ conductivity region, the channel region of the power device having a root mean square (RMS) surface roughness of less than about 1.0 ?.

Abstract: Methods for fabricating LED packages comprising providing an LED chip and covering at least part of it with a liquid medium. An optical element is provided and placed on the liquid medium. The optical element is allowed to settle to a desired level and the liquid medium is cured. LED packages are also disclosed that are fabricated using the disclosed methods.

Abstract: Power devices are provided including a p-type conductivity well region and a buried p+ conductivity region in the p-type conductivity well region. An n+ conductivity region is provided on the buried p+ conductivity region. A channel region of the power device is provided adjacent the buried p+ conductivity region and n+ conductivity region, the channel region of the power device having a root mean square (RMS) surface roughness of less than about 1.0 ?.

Abstract: Methods of forming silicon carbide power devices are provided. An n? silicon carbide layer is provided on a silicon carbide substrate. A p-type silicon carbide well region is provided on the n? silicon carbide layer. A buried region of p+ silicon carbide is provided on the p-type silicon carbide well region. An n+ region of silicon carbide is provided on the buried region of p+ silicon carbide. A channel region of the power device is adjacent the buried region of p+ silicon carbide and the n+ region of silicon carbide. An n? region is provided on the channel region and a portion of the n? region is removed from the channel region so that a portion of the n? region remains on the channel region to provide a reduction in a surface roughness of the channel region.

Abstract: A high quality single crystal wafer of SiC is disclosed. The wafer has a diameter of at least about 3 inches, a warp of less than about 5 ?m, a bow less than about 5 ?m, and a total thickness variation of less than about 2.0 ?m.

Abstract: Olefinic interpolymer compositions comprising the olefinic interpolymer, residuals from a transition metal catalyst and boron containing activator package, and a charge dissipation modifier and methods for making them. The compositions have dissipation factors that are at least 50% less than the corresponding olefinic interpolymer compositions which have not been treated with charge dissipation modifiers. The compositions are useful in wire and cable applications.

Abstract: Shear-thinning ethylene/?-olefin and ethylene/?-olefin/diene monomer interpolymers that do not include a traditional branch-inducing monomer such as norbornadiene are prepared at an elevated temperature in an atmosphere that has little or no hydrogen using a constrained geometry complex catalyst and an activating cocatalyst.

Abstract: Olefinic interpolymer compositions comprising the olefinic interpolymer, residuals from a transition metal catalyst and boron containing activator package, and a charge dissipation modifier and methods for making them. The compositions have dissipation factors that are at least 50% less than the corresponding olefinic interpolymer compositions which have not been treated with charge dissipation modifiers. The compositions are useful in wire and cable applications.

Abstract: Methods of forming silicon carbide power devices are provided. An n? silicon carbide layer is provided on a silicon carbide substrate. A p-type silicon carbide well region is provided on the n? silicon carbide layer. A buried region of p+ silicon carbide is provided on the p-type silicon carbide well region. An n+ region of silicon carbide is provided on the buried region of p+ silicon carbide. A channel region of the power device is adjacent the buried region of p+ silicon carbide and the n+ region of silicon carbide. An n? region is provided on the channel region and a portion of the n? region is removed from the channel region so that a portion of the n? region remains on the channel region to provide a reduction in a surface roughness of the channel region.

Abstract: A high quality single crystal wafer of SiC is disclosed. The wafer has a diameter of at least about 3 inches, a warp of less than about 5 ?m, a bow less than about 5 ?m, and a total thickness variation of less than about 2.0 ?m.