Patents by Inventor Michael Launsbach
Michael Launsbach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9312858Abstract: A level shifter circuit for coupling a first circuit, that uses a first supply voltage, with a second circuit, that uses a second supply voltage, includes an input node to receive an input signal and an output node to output to a level-shifted output signal corresponding with the input signal. An idle state on the input node corresponds with a particular binary logic value that is maintained for a first time period, and which is detected by a detection sub-circuit. Further, the level shifter circuit includes a first inverter that uses the second supply voltage, and has a feedback path between the input and output of the first inverter. The feedback path includes a first resistive element and a first transmission gate. The first transmission gate is configurable to open the feedback path when the detection sub-circuit detects an idle state on the input node of the level shifter circuit.Type: GrantFiled: June 2, 2014Date of Patent: April 12, 2016Assignee: International Business Machines CorporationInventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach
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Patent number: 9287873Abstract: A level shifter circuit for coupling a first circuit, that uses a first supply voltage, with a second circuit, that uses a second supply voltage, includes an input node to receive an input signal and an output node to output to a level-shifted output signal corresponding with the input signal. An idle state on the input node corresponds with a particular binary logic value that is maintained for a first time period, and which is detected by a detection sub-circuit. Further, the level shifter circuit includes a first inverter that uses the second supply voltage, and has a feedback path between the input and output of the first inverter. The feedback path includes a first resistive element and a first transmission gate. The first transmission gate is configurable to open the feedback path when the detection sub-circuit detects an idle state on the input node of the level shifter circuit.Type: GrantFiled: August 20, 2014Date of Patent: March 15, 2016Assignee: International Business Machines CorporationInventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach
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Patent number: 9218880Abstract: A TCAM may have a plurality of rows of cells. Each row may have a match line. Each cell may have elements for storing first and second bits, and compare circuitry associated to determine matches between a bit of a search word and data stored in the cell. For at least one first row of the rows, the TCAM includes a valid row cell having at least one element to store a partial update indication. The valid row cell may cause the match line associated with the first row to signal that the first row does not match a search word when the partial update indication associated with the first row is enabled. When the partial update indication associated with the first row is disabled, the determination of matches with a search word is performed solely by the compare circuitry without influence of the valid row cell.Type: GrantFiled: May 20, 2014Date of Patent: December 22, 2015Assignee: International Business Machines CorporationInventors: Igor Arsovski, Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach
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Publication number: 20150349779Abstract: A level shifter circuit for coupling a first circuit, that uses a first supply voltage, with a second circuit, that uses a second supply voltage, includes an input node to receive an input signal and an output node to output to a level-shifted output signal corresponding with the input signal. An idle state on the input node corresponds with a particular binary logic value that is maintained for a first time period, and which is detected by a detection sub-circuit. Further, the level shifter circuit includes a first inverter that uses the second supply voltage, and has a feedback path between the input and output of the first inverter. The feedback path includes a first resistive element and a first transmission gate. The first transmission gate is configurable to open the feedback path when the detection sub-circuit detects an idle state on the input node of the level shifter circuit.Type: ApplicationFiled: August 20, 2014Publication date: December 3, 2015Inventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach
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Publication number: 20150349778Abstract: A level shifter circuit for coupling a first circuit, that uses a first supply voltage, with a second circuit, that uses a second supply voltage, includes an input node to receive an input signal and an output node to output to a level-shifted output signal corresponding with the input signal. An idle state on the input node corresponds with a particular binary logic value that is maintained for a first time period, and which is detected by a detection sub-circuit. Further, the level shifter circuit includes a first inverter that uses the second supply voltage, and has a feedback path between the input and output of the first inverter. The feedback path includes a first resistive element and a first transmission gate. The first transmission gate is configurable to open the feedback path when the detection sub-circuit detects an idle state on the input node of the level shifter circuit.Type: ApplicationFiled: June 2, 2014Publication date: December 3, 2015Applicant: International Business Machines CorporationInventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach
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Patent number: 9196671Abstract: A semiconductor device may include a through substrate via (TSV) conductive structure that may extend vertically through two or more layers of the semiconductor device. The TSV conductive structure may be coupled to a first voltage supply. The semiconductor device may include substrate layer. The substrate layer may include a first dopant region and a second dopant region. The first dopant region may be coupled to a second voltage supply. The second dopant region may be in electrical communication with the TSV conductive structure. The semiconductor device may include a first metal layer and a first insulator layer disposed between the substrate layer and the first metal layer. The first metal layer may laterally contact the TSV conductive structure. The first and second voltage supply may be adapted to create a capacitance at a junction between the first dopant region and the second dopant region.Type: GrantFiled: November 2, 2012Date of Patent: November 24, 2015Assignee: International Business Machines CorporationInventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach, John E. Sheets, II
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Patent number: 9153638Abstract: A semiconductor device may include a through substrate via (TSV) conductive structure that may extend vertically through two or more layers of the semiconductor device. The TSV conductive structure may be coupled to a first voltage supply. The semiconductor device may include substrate layer. The substrate layer may include a first dopant region and a second dopant region. The first dopant region may be coupled to a second voltage supply. The second dopant region may be in electrical communication with the TSV conductive structure. The semiconductor device may include a first metal layer and a first insulator layer disposed between the substrate layer and the first metal layer. The first metal layer may laterally contact the TSV conductive structure. The first and second voltage supply may be adapted to create a capacitance at a junction between the first dopant region and the second dopant region.Type: GrantFiled: February 11, 2013Date of Patent: October 6, 2015Assignee: International Business Machines CorporationInventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach, John E. Sheets, II
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Patent number: 9142560Abstract: A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.Type: GrantFiled: August 18, 2014Date of Patent: September 22, 2015Assignee: International Business Machines CorporationInventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach, Daniel M. Nelson
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Patent number: 9082484Abstract: A TCAM may have a plurality of rows of cells. Each row may have a match line. Each cell may have elements for storing first and second bits, and compare circuitry associated to determine matches between a bit of a search word and data stored in the cell. For at least one first row of the rows, the TCAM includes a valid row cell having at least one element to store a partial update indication. The valid row cell may cause the match line associated with the first row to signal that the first row does not match a search word when the partial update indication associated with the first row is enabled. When the partial update indication associated with the first row is disabled, the determination of matches with a search word is performed solely by the compare circuitry without influence of the valid row cell.Type: GrantFiled: December 23, 2013Date of Patent: July 14, 2015Assignee: International Business Machines CorporationInventors: Igor Arsovski, Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach
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Publication number: 20150179262Abstract: A TCAM may have a plurality of rows of cells. Each row may have a match line. Each cell may have elements for storing first and second bits, and compare circuitry associated to determine matches between a bit of a search word and data stored in the cell. For at least one first row of the rows, the TCAM includes a valid row cell having at least one element to store a partial update indication. The valid row cell may cause the match line associated with the first row to signal that the first row does not match a search word when the partial update indication associated with the first row is enabled. When the partial update indication associated with the first row is disabled, the determination of matches with a search word is performed solely by the compare circuitry without influence of the valid row cell.Type: ApplicationFiled: December 23, 2013Publication date: June 25, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Igor Arsovski, Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach
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Publication number: 20150179261Abstract: A TCAM may have a plurality of rows of cells. Each row may have a match line. Each cell may have elements for storing first and second bits, and compare circuitry associated to determine matches between a bit of a search word and data stored in the cell. For at least one first row of the rows, the TCAM includes a valid row cell having at least one element to store a partial update indication. The valid row cell may cause the match line associated with the first row to signal that the first row does not match a search word when the partial update indication associated with the first row is enabled. When the partial update indication associated with the first row is disabled, the determination of matches with a search word is performed solely by the compare circuitry wi thout influence of the valid row cell.Type: ApplicationFiled: May 20, 2014Publication date: June 25, 2015Applicant: International Business Machines CorporationInventors: Igor Arsovski, Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach
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Patent number: 9058861Abstract: A static random access memory (SRAM) having two or more SRAM memory cells connected with a write bit line (WBL) and a write bit line complement (WBLC) is disclosed. The SRAM may include a write driver logic coupled to the WBL and the WBLC. The write driver logic is adapted to drive a selected bit line of the WBL and the WBLC to a voltage uplevel below a first supply voltage and shut off the drive to the selected bit line when the selected bit line reaches the uplevel. The write driver logic is further adapted to drive an unselected bit line of the WBL and the WBLC to a downlevel, in conjunction with the driving of the selected bit line to the uplevel, where the downlevel is a second supply voltage lower than the first supply voltage.Type: GrantFiled: December 18, 2012Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach
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Publication number: 20140353764Abstract: A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.Type: ApplicationFiled: August 18, 2014Publication date: December 4, 2014Inventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach, Daniel M. Nelson
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Patent number: 8860141Abstract: A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.Type: GrantFiled: January 6, 2012Date of Patent: October 14, 2014Assignee: International Business Machines CorporationInventors: Derick Gardner Behrends, Todd Alan Christensen, Travis Reynold Hebig, Michael Launsbach, Daniel Mark Nelson
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Publication number: 20140293679Abstract: An embodiment of the current disclosure is directed to a Static Random Access Memory (SRAM) device, and a design structure for the SRAM device. The SRAM device may include one or more SRAM cells. Each SRAM cell may further include a first and a second CMOS inverter that are cross-coupled. The first and second CMOS inverters may each have a first switch and a second switch. The SRAM device may also include a reset circuit. The reset circuit may be coupled to a first node of the first switch of the first CMOS inverter. The reset circuit may drive the first CMOS inverter to output a logical high signal in a reset mode.Type: ApplicationFiled: March 26, 2013Publication date: October 2, 2014Applicant: International Business Machines CorporationInventors: Derick G. Behrends, Todd A. Christensen, Michael W. Harper, Travis R. Hebig, Michael Launsbach
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Patent number: 8842487Abstract: A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line. In addition the SRAM may include a global bit line discharge logic connected with the global bit line and the local bit line. The global bit line discharge logic is adapted to draw the global bit line to a voltage below a precharge voltage and above a ground voltage during a read operation.Type: GrantFiled: February 26, 2013Date of Patent: September 23, 2014Assignee: International Business Machines CorporationInventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach
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Patent number: 8824196Abstract: A static random access memory (SRAM) includes a column of SRAM memory cells. The SRAM may include a circuit to copy a value stored in any SRAM memory cell in a column of SRAM memory cells to any SRAM memory cell in the column of SRAM memory cells in a single cycle of the SRAM.Type: GrantFiled: March 30, 2012Date of Patent: September 2, 2014Assignee: International Business Machines CorporationInventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach, Daniel M. Nelson
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Publication number: 20140169076Abstract: A static random access memory (SRAM) having two or more SRAM memory cells connected with a write bit line (WBL) and a write bit line complement (WBLC) is disclosed. The SRAM may include a write driver logic coupled to the WBL and the WBLC. The write driver logic is adapted to drive a selected bit line of the WBL and the WBLC to a voltage uplevel below a first supply voltage and shut off the drive to the selected bit line when the selected bit line reaches the uplevel. The write driver logic is further adapted to drive an unselected bit line of the WBL and the WBLC to a downlevel, in conjunction with the driving of the selected bit line to the uplevel, where the downlevel is a second supply voltage lower than the first supply voltage.Type: ApplicationFiled: December 18, 2012Publication date: June 19, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach
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Publication number: 20140127875Abstract: A semiconductor device may include a through substrate via (TSV) conductive structure that may extend vertically through two or more layers of the semiconductor device. The TSV conductive structure may be coupled to a first voltage supply. The semiconductor device may include substrate layer. The substrate layer may include a first dopant region and a second dopant region. The first dopant region may be coupled to a second voltage supply. The second dopant region may be in electrical communication with the TSV conductive structure. The semiconductor device may include a first metal layer and a first insulator layer disposed between the substrate layer and the first metal layer. The first metal layer may laterally contact the TSV conductive structure. The first and second voltage supply may be adapted to create a capacitance at a junction between the first dopant region and the second dopant region.Type: ApplicationFiled: February 11, 2013Publication date: May 8, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach, John E. Sheets, II
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Publication number: 20140126276Abstract: A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a precharge device connected between a voltage supply and the local bit line, and global bit line (GBL) discharge logic connected between a local bit line and a GBL. The GBL discharge logic transfers a logic value of the local bit line to the GBL during a read operation. GBL precharge logic connects the GBL to a global precharge input. The GBL precharge logic is adapted to draw the GBL to a precharge voltage above a discharge voltage and below a supply voltage during a precharge operation.Type: ApplicationFiled: February 27, 2013Publication date: May 8, 2014Applicant: International Business Machines CorporationInventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach