Abstract: A waffle iron comprises textured upper, lower, and perimeter heatable plates that can be assembled to create a cavity into which batter and other prepared ingredients are dispensed to cook a waffle having sufficient depth to feature a waffle pattern along its top and bottom faces as well as along its thickness and to fully contain within its batter separate, prepared ingredients which are enclosed within the waffle to make a single unit and can be eaten in its entirety by hand without having to fold the waffle around those ingredients, sandwich those ingredients between waffles, or use any other means to keep the waffle from separating from the ingredients. The waffle can be visually inspected for doneness during the cooking process or removed from the assembled unit once cooked by separating the individual plates. Electronic means may also be employed to monitor or alert of doneness.

Abstract: A waffle iron comprises textured upper, lower, and perimeter heatable plates that can be assembled to create a cavity into which batter and other prepared ingredients are dispensed to cook a waffle having sufficient depth to feature a waffle pattern along its top and bottom faces as well as along its thickness and to fully contain within its batter separate, prepared ingredients which are enclosed within the waffle to make a single unit and can be eaten in its entirety by hand without having to fold the waffle around those ingredients, sandwich those ingredients between waffles, or use any other means to keep the waffle from separating from the ingredients. The waffle can be visually inspected for doneness during the cooking process or removed from the assembled unit once cooked by separating the individual plates. Electronic means may also be employed to monitor or alert of doneness.

Abstract: A system including a receiver, a TMDS link (or other serial link), and a transmitter configured to transmit K-bit video words (typically, encoded 8-bit video words) over the link. In typical embodiments, the transmitter is configured to pack a sequence of N-bit video words, where N?K (e.g., N=10, 12, or 16, when K=8) into a sequence of K-bit fragments, encode the fragments, and transmit the encoded fragments. The transmitted data are indicative of a sequence of M-fragment groups, and the transmitter is typically configured also to transmit over the link packing phase data indicative of the phase of the most recently transmitted fragment. Other aspects are transmitters and receivers for use in such a system and methods implemented by any such transmitter, receiver, or system.

Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).

Abstract: A real estate sign post is comprised of three principal components, namely a lower PVC tubular member vertically connected to a PVC cross tee and an upper PVC tubular member that is horizontally connected to said cross tee. Also attached to the horizontal PVC tubular member are a set of eyebolts and S-hooks to attach a hanging realtor sign. The third PVC tubular member is to be placed in the ground vertically and affixed to the lower end of the vertical tube member of the sign post to firmly support the sign post at the property.

Abstract: A fast frame buffer system and architecture supports preferably 24-bit capability and includes an integer rendering pipeline, especially useful for three-dimensional applications. The system includes a frame buffer random access memory system ("FBRAM") that includes video source data and is configurable as a single-buffer or double-buffer, a fast frame buffer controller integrated circuit ("FFB ASIC") that includes system command and video refresh control functions, and a random access memory digital-to-analog converter unit ("RAMDAC") that includes the buffer system timing generator. A FBRAM controller unit provides both parallel accelerated rendering pipeline and direct access paths to the FBRAM unit. The timing generator outputs serial clock and serial clock enable signals, the latter signal preceding horizontal blanking signals by preferably N=1 serial clock pulses to compensate for pixel signal path timing delays.