Abstract: A method of encoding a stream of data bits includes encoding a bit 1 of the data stream as a first symbol if a bit immediately preceding the bit 1 is encoded as 0 and a bit of the data stream immediately succeeding the bit 1 is 0, encoding the bit immediately succeeding the bit 1 as 1, encoding a bit 0 of the data stream as a second symbol if a bit immediately preceding the bit 0 is encoded as 1 and a bit of the data stream immediately succeeding the bit 0 is 1, and encoding the bit immediately succeeding the bit 0 as 0.

Abstract: A method of encoding a stream of data bits includes encoding a bit 1 of the data stream as a first symbol if a bit immediately preceding the bit 1 is encoded as 0 and a bit of the data stream immediately succeeding the bit 1 is 0, encoding the bit immediately succeeding the bit 1 as 1, encoding a bit 0 of the data stream as a second symbol if a bit immediately preceding the bit 0 is encoded as 1 and a bit of the data stream immediately succeeding the bit 0 is 1, and encoding the bit immediately succeeding the bit 0 as 0.

Abstract: A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.

Abstract: A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.

Abstract: A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.

Abstract: A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.

Abstract: A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.

Abstract: A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.

Abstract: A Constant Velocity Vector Generator is disclosed for connecting X, Y coordinate points of a rectangular coordinate display system. A pair of absolute value amplifier circuits, a square-root-of-the-sum-of-the-squares circuit, a pair of dividers, and a pair of integrators are employed to convert simultaneous .DELTA.X and .DELTA.Y step voltages to ramp voltage pairs which are applied to appropriate X and Y deflection circuits of a graphic display device to produce straight-line traces whose velocities are constant for all vectors regardless of magnitude (line length) or direction (angle). Each vector may be drawn to any length or direction, immediately after which new data may be applied to the vector generator to initiate a new vector whose origin is the end point of the preceding vector. Such a system is particularly applicable to computer-drawn displays. The vector generating circuits are suitable for realization in a monolithic integrated circuit.

Abstract: A Constant Velocity Vector Generator is disclosed for connecting X, Y coordinate points of a rectangular coordinate display system. A pair of absolute value amplifier circuits, a square-root-of-the-sum-of-the-squares circuit, a pair of dividers, and a pair of integrators are employed to convert simultaneous .DELTA.X and .DELTA.Y step voltages to ramp voltage pairs which are applied to appropriate X and Y deflection circuits of a graphic display device to produce straight-line traces whose velocities are constant for all vectors regardless of magnitude (line length) or direction (angle). Each vector may be drawn to any length or direction, immediately after which new data may be applied to the vector generator to initiate a new vector whose origin is the end point of the preceding vector. Such a system is particularly applicable to computer-drawn displays. The vector generating circuits are suitable for realization in a monolithic integrated circuit.

Abstract: A circuit to correct for pincushion distortion and defocusing in a cathode-ray tube having electromagnetic deflection systems is disclosed. The circuit, which may be realized in monolithic integrated-circuit form, performs a mathematical function to predistort the deflection signal for each axis by the amount necessary to provide an undistorted display. The circuit also provides a signal to correct for the defocusing that occurs at the edges of the screen. The circuit may be readily adapted for use with cathode-ray tubes having different diagonal deflection angles, and with either flat of curved faceplates, by changing the values of two resistors.

Abstract: A Constant Velocity Vector Generator is disclosed for connecting X, Y coordinate points of a rectangular coordinate display system. Simultaneous .DELTA.X and .DELTA.Y step voltages are converted to ramp voltage pairs which are applied to appropriate X and Y deflection circuits of a graphic display device to produce straight-line traces whose velocities are constant for all vectors regardless of magnitude (line length) or direction (angle). Each vector may be drawn to any length or direction, immediately after which new data may be applied to the vector generator to initiate a new vector whose origin is the end point of the preceding vector. Such a system is particularly applicable to computer-drawn displays. The vector generating circuits are suitable for realization in a monolithic integrated circuit.