Abstract: In a vertical deflection circuit, a deflection winding is coupled to an output terminal of a deflection amplifier. The amplifier generates a trace current in the winding in response to drive signals coupled to an input terminal of the amplifier. A first voltage source provides an operating voltage for the amplifier. A bidirectional retrace switch couples the output terminal to a second voltage source for providing a greater magnitude voltage for generating a retrace current in the winding. The bidirectional switch has a controlled semiconductor which is responsive to the drive signals for controlling a main conductive path of the switch during a portion of the retrace interval.

Abstract: A convergence circuit coupled in parallel with a deflection winding are AC coupled to an output terminal of a deflection amplifier. Rectifiers in the convergence circuit are poled such that the deflection amplifier output current is assymmetrically loaded during the trace portion of each deflection cycle, causing a net direct current of a first polarity through the deflection winding which off-centers the raster. A direct current path coupled in shunt with the yoke coupling capacitor permits conduction of a direct current of a second polarity through the deflection winding for controlling the centering of the raster.

Abstract: A deflection system, utilizing a deflection generator coupled to a deflection winding to provide a current in the deflection winding having a magnitude which is a function of the elasped time after a retrace pulse and which changes substantially linearly, includes a retrace pulse generator. The retrace pulse generator utilizes a first gating circuit to provide for controllable coupling between a source of trigger pulses having a first time interval therebetween and a first monostable retrace pulse generator circuit. Fixed width retrace pulses are thereby generated in response to trigger pulses. A second monostable circuit responsive to the retrace pulses is coupled to the first gate for inhibiting the flow of pulses through the first gate for a second interval of time which is less than the first interval of time. The first monostable circuit is therefore immune to noise pulses occurring during the second interval of time.