Patents by Inventor Michael Lewis Takefman
Michael Lewis Takefman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230185757Abstract: A multi-lane integrated circuit transceiver device includes first and second integrated circuit dies having respective first and second pluralities of transmit block/receive block pairs. Each respective transmit block and each respective receive block in the first plurality of block pairs on the first die and the second plurality of block pairs on the second die includes respective digital clock generation circuitry. The device further includes digital clock distribution circuitry to distribute a digital clock signal output by one respective receive block, in one of the first and second pluralities of block pairs, to the transmit blocks in both of the pluralities of block pairs, for use as a baseline clock by the respective digital clock generation circuitry in each of the transmit blocks in both of the pluralities of block pairs. Where each plurality includes N block pairs, the two dies together form a single 2N-lane device.Type: ApplicationFiled: December 8, 2022Publication date: June 15, 2023Inventors: Michael Lewis Takefman, Arash Farhoodfar, Srinivas Swaminathan, Belal Helal
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Patent number: 9465557Abstract: A load reduction dual in-line memory module (LRDIMM) is similar to a registered dual in-line memory module (RDIMM) in which control signals are synchronously buffered but the LRDIMM includes a load reduction buffer (LRB) in the data path as well. To make an LRDIMM which appears compatible with RDIMMs on a system memory bus, the serial presence detector (SPD) of the LRDIMM is programmed with modified latency support and minimum delay values. When the dynamic read only memory (DRAMs) devices of the LRDIMM are subsequently set up by the host at boot time based on the parameters provided by the SPD, selected latency values are modified on the fly in an enhanced register phase look loop (RPLL) device. This has the effect of compensating for the delay introduced by the LRB without violating DRAM constraints, and provides memory bus timing for a LRDIMM that is indistinguishable from that of a RDIMM.Type: GrantFiled: April 20, 2015Date of Patent: October 11, 2016Assignee: DIABLO TECHNOLOGIES INC.Inventors: Maher Amer, Michael Lewis Takefman
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Publication number: 20150227324Abstract: A load reduction dual in-line memory module (LRDIMM) is similar to a registered dual in-line memory module (RDIMM) in which control signals are synchronously buffered but the LRDIMM includes a load reduction buffer (LRB) in the data path as well. To make an LRDIMM which appears compatible with RDIMMs on a system memory bus, the serial presence detector (SPD) of the LRDIMM is programmed with modified latency support and minimum delay values. When the dynamic read only memory (DRAMs) devices of the LRDIMM are subsequently set up by the host at boot time based on the parameters provided by the SPD, selected latency values are modified on the fly in an enhanced register phase look loop (RPLL) device. This has the effect of compensating for the delay introduced by the LRB without violating DRAM constraints, and provides memory bus timing for a LRDIMM that is indistinguishable from that of a RDIMM.Type: ApplicationFiled: April 20, 2015Publication date: August 13, 2015Inventors: Maher Amer, Michael Lewis Takefman
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Patent number: 9015408Abstract: A method is disclosed for providing memory bus timing of a load reduction dual inline memory module (LRDIMM). The method includes: determining a latency value of a dynamic random access memory (DRAM) of the LRDIMM; determining a modified latency value of the DRAM that accounts for a delay caused by a load reduction buffer (LRB) that is deployed between the DRAM and a memory bus; storing the modified latency value in a serial presence detector (SPD) of the LRDIMM; and providing memory bus timing for the LRDIMM based on the modified latency value, wherein the memory bus timing is compatible with a registered dual inline memory module (RDIMM).Type: GrantFiled: May 5, 2014Date of Patent: April 21, 2015Assignee: Diablo Technologies, Inc.Inventors: Maher Amer, Michael Lewis Takefman
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Publication number: 20140244924Abstract: A method is disclosed for providing memory bus timing of a load reduction dual inline memory module (LRDIMM). The method includes: determining a latency value of a dynamic random access memory (DRAM) of the LRDIMM; determining a modified latency value of the DRAM that accounts for a delay caused by a load reduction buffer (LRB) that is deployed between the DRAM and a memory bus; storing the modified latency value in a serial presence detector (SPD) of the LRDIMM; and providing memory bus timing for the LRDIMM based on the modified latency value, wherein the memory bus timing is compatible with a registered dual inline memory module (RDIMM).Type: ApplicationFiled: May 5, 2014Publication date: August 28, 2014Applicant: DIABLO TECHNOLOGIES INC.Inventors: Maher Amer, Michael Lewis Takefman
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Patent number: 8738853Abstract: A load reduction dual in-line memory module (LRDIMM) is similar to a registered dual inline memory module (RDIMM) in which control signals are synchronusly buffered but the LRDIMM includes a load reduction buffer (LRB) in the data path as well. To make an LRDIMM which appears compatible with RDIMMs on a system memory bus, the serial presence detector (SPD) of the LRDIMM is programmed with modified latency support and minimum delay values. When the dynamic read only memory (DRAMs) devices of the LRDIMM are subsequently set up by the host at boot time based on the parameters provided by the SPD, selected latency values are modified on the fly in an enhanced register phase look loop (RPLL) device. This has the effect of compensating for the delay introduced by the LRB without violating DRAM constraints, and provides memory bus timing for a LRDIMM that is indistinguishable from that of a RDIMM.Type: GrantFiled: April 30, 2013Date of Patent: May 27, 2014Assignee: Diablo Technologies Inc.Inventors: Maher Amer, Michael Lewis Takefman
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Publication number: 20130238849Abstract: A load reduction dual in-line memory module (LRDIMM) is similar to a registered dual inline memory module (RDIMM) in which control signals are synchronusly buffered but the LRDIMM includes a load reduction buffer (LRB) in the data path as well. To make an LRDIMM which appears compatible with RDIMMs on a system memory bus, the serial presence detector (SPD) of the LRDIMM is programmed with modified latency support and minimum delay values. When the dynamic read only memory (DRAMs) devices of the LRDIMM are subsequently set up by the host at boot time based on the parameters provided by the SPD, selected latency values are modified on the fly in an enhanced register phase look loop (RPLL) device. This has the effect of compensating for the delay introduced by the LRB without violating DRAM constraints, and provides memory bus timing for a LRDIMM that is indistinguishable from that of a RDIMM.Type: ApplicationFiled: April 30, 2013Publication date: September 12, 2013Applicant: DIABLO TECHNOLOGIES INC.Inventors: Maher Amer, Michael Lewis Takefman
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Patent number: 8452917Abstract: A load reduction dual in-line memory module (LRDIMM) is similar to a registered dual in-line memory module (RDIMM) in which control signals are synchronously buffered but the LRDIMM includes a load reduction buffer (LRB) in the data path as well. To make an LRDIMM which appears compatible with RDIMMs on a system memory bus, the serial presence detector (SPD) of the LRDIMM is programmed with modified latency support and minimum delay values. When the dynamic read only memory (DRAMs) devices of the LRDIMM are subsequently set up by the host at boot time based on the parameters provided by the SPD, selected latency values are modified on the fly in an enhanced register phase look loop (RPLL) device. This has the effect of compensating for the delay introduced by the LRB without violating DRAM constraints, and provides memory bus timing for a LRDIMM that is indistinguishable from that of a RDIMM.Type: GrantFiled: September 14, 2009Date of Patent: May 28, 2013Assignee: Diablo Technologies Inc.Inventors: Maher Amer, Michael Lewis Takefman
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Patent number: 7742410Abstract: Methods and apparatus are disclosed for using gap packets to create a bandwidth buffer over which packets can be sent to reduce or eliminate overflow conditions. One implementation sends a series of packets from a first device to a second device, the series of packets including interspersed information packets and gap packets. The first device determines when to insert the gap packets into the series of packets, and the gap packets received by the second device are dropped. The determination of when to insert one of the gap packets into the series of packets may be based on an occupancy level of a buffer, such as, but not limited to comparing it to a predetermined or variable threshold value. Also, the rate of sending gap packets and/or the size of the gap packets may be varied to adjust the size of bandwidth buffer created by the gap packets.Type: GrantFiled: December 16, 2002Date of Patent: June 22, 2010Assignee: Cisco Technology, Inc.Inventors: Leonid Goldin, Michael Lewis Takefman
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Publication number: 20100070690Abstract: A load reduction dual in-line memory module (LRDIMM) is similar to a registered dual in-line memory module (RDIMM) in which control signals are synchronously buffered but the LRDIMM includes a load reduction buffer (LRB) in the data path as well. To make an LRDIMM which appears compatible with RDIMMs on a system memory bus, the serial presence detector (SPD) of the LRDIMM is programmed with modified latency support and minimum delay values. When the dynamic read only memory (DRAMs) devices of the LRDIMM are subsequently set up by the host at boot time based on the parameters provided by the SPD, selected latency values are modified on the fly in an enhanced register phase look loop (RPLL) device. This has the effect of compensating for the delay introduced by the LRB without violating DRAM constraints, and provides memory bus timing for a LRDIMM that is indistinguishable from that of a RDIMM.Type: ApplicationFiled: September 14, 2009Publication date: March 18, 2010Inventors: Maher Amer, Michael Lewis Takefman
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Patent number: 7453873Abstract: Methods and apparatus are disclosed for identifying the relevancy of packets. In one embodiment, source addresses are associated with network topology indications. When a packet is received, its network topology indication is compared with the corresponding one retrieved from a data structure to determine whether to drop the packet. Source addresses may also be associated with authorized interfaces to determine whether a packet was received on an authorized interface. In one embodiment, a maintained network topology indication is associated with a packet. After it is processed, the corresponding latest network topology indication is retrieved and compared with that previously associated with the packet. In one embodiment, upon a change in a network topology indication associated with an interface, control packets are placed in each of the queues corresponding to the destination interface, so it can be readily identified when this update has been propagated through the system.Type: GrantFiled: May 13, 2003Date of Patent: November 18, 2008Assignee: Cisco Technology, Inc.Inventors: Michael Lewis Takefman, Leonid Goldin
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Patent number: 5761197Abstract: A central station of a cable television distribution network transmits TDM frames comprising distribution information and overhead information downstream to customer terminals, and determines corresponding upstream TDMA frames by including an upstream frame identity in the overhead information of each downstream frame. Each terminal buffers asynchronous information for upstream transmission, and stores an upstream frame identity which it is assigned. On detecting this frame identity in the downstream overhead information, the terminal transmit a buffer queue size in an assigned time slot of the corresponding upstream frame. The central station uses the queue sizes from the terminals to allocate time slots in the upstream frames to terminals, by including their terminal addresses in the downstream overhead information, for transmission of the buffered asynchronous information. The central station can also assign time slots to the terminals for transmission of isochronous information.Type: GrantFiled: November 14, 1994Date of Patent: June 2, 1998Assignee: Northern Telecom LimitedInventor: Michael Lewis Takefman