Abstract: A technique that unfolds the nMOS-tree multiplexer to improve the propagation delay and/or active power consumption is provided. The main idea is to replicate the nMOS element of the downstream buffer, where each replica is driven by a signal that originates from earlier stages of the nMOS-tree multiplexer. This way, when passing high logic values, signals from earlier stages directly drive the downstream buffer improving the delay or the slope of the transition edge (with beneficial effects for power consumption). The passing of low logic values is still performed in the original way by the nMOS tree and the pMOS element of the downstream buffer.

Abstract: A coarse-grain reconfigurable array that implements shift operations within its interconnection network is disclosed. The interconnection network of such a coarse-grain reconfigurable array contains partially or fully populated matrices of switches, where each such matrix of switches is obtained by merging a standard diagonal switch matrix with an array shift unit. The disclosed device provides better performance when the standard routing and shift functions are both required.

Abstract: A technique that unfolds the nMOS-tree multiplexer to improve the propagation delay and/or active power consumption is provided. The main idea is to replicate the nMOS element of the downstream buffer, where each replica is driven by a signal that originates from earlier stages of the nMOS-tree multiplexer. This way, when passing high logic values, signals from earlier stages directly drive the downstream buffer improving the delay or the slope of the transition edge (with beneficial effects for power consumption). The passing of low logic values is still performed in the original way by the nMOS tree and the pMOS element of the downstream buffer.