Abstract: Described embodiments include a rectifier circuit comprising a first resistor with first and second resistor terminals, and a second resistor with third and fourth resistor terminals. The first and third resistor terminals are coupled to an auxiliary power terminal. A current source is coupled between the second resistor terminal and a ground terminal. An amplifier has a first amplifier input coupled to the second resistor terminal, and a second amplifier input coupled to the fourth resistor terminal. A first transistor is coupled between the fourth resistor terminal and a damping terminal, and has a first control terminal coupled to the first amplifier output. A gate drive circuit has an input coupled to the damping terminal. A second transistor is coupled between the damping terminal and a bootstrap supply terminal, and has a second control terminal coupled to an output of the gate drive circuit.

Abstract: The present disclosure generally relates to a semiconductor device having a slanted field plate. In an example, a semiconductor device includes a semiconductor substrate, a gate, a drain contact, a source contact, and a field plate. The gate is on a surface of the semiconductor substrate. The drain contact and a source contact are on the semiconductor substrate. The field plate is over the surface of the semiconductor substrate and extends from one side of the gate towards the drain contact. The field plate includes multiple field plate portions. Each of the multiple field plate portions has a uniform respective slope with respect to the surface, and the multiple field plate portions have different slopes.

Abstract: An apparatus includes a first transistor having a first transistor control terminal and coupled between a power terminal and a switching terminal. The apparatus further includes a second transistor having a second transistor control terminal and coupled between the switching terminal and a ground terminal. The apparatus further includes a first switch coupled between the power terminal and the second transistor control terminal, the first switch having a first switch control terminal; The apparatus further includes a second switch coupled between the second control terminal and the ground terminal, the second switch having a second switch control terminal. The apparatus also includes a controller having a control input, a first control output, and a second control output, the control input coupled to the second transistor control terminal, the first control output coupled to the first switch control terminal, and the second control output coupled to the second switch control terminal.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.

Abstract: The present invention provides a capacitor having a first structure made of a metal layer and a second structure made of the same metal layer and a dielectric layer between the first and the second metal structure, wherein the dielectric layer has a relative permittivity greater than 4, in particular greater than 6. It also provides a monolithically integrated circuit including such a capacitor and optionally other components. A method of manufacturing such a capacitor is also provided.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.

Abstract: Described embodiments include a rectifier circuit comprising a first resistor with first and second resistor terminals, and a second resistor with third and fourth resistor terminals. The first and third resistor terminals are coupled to an auxiliary power terminal. A current source is coupled between the second resistor terminal and a ground terminal. An amplifier has a first amplifier input coupled to the second resistor terminal, and a second amplifier input coupled to the fourth resistor terminal. A first transistor is coupled between the fourth resistor terminal and a damping terminal, and has a first control terminal coupled to the first amplifier output. A gate drive circuit has an input coupled to the damping terminal. A second transistor is coupled between the damping terminal and a bootstrap supply terminal, and has a second control terminal coupled to an output of the gate drive circuit.

Abstract: The present invention provides a capacitor having a first structure made of a metal layer and a second structure made of the same metal layer and a dielectric layer between the first and the second metal structure, wherein the dielectric layer has a relative permittivity greater than 4, in particular greater than 6. It also provides a monolithically integrated circuit including such a capacitor and optionally other components. A method of manufacturing such a capacitor is also provided.

Abstract: A self-biasing circuit for power converters is disclosed. In an example, an apparatus includes a first transistor coupled between an inductor terminal and a ground terminal, and a second transistor coupled between the inductor terminal and a bias terminal. The first transistor has a first control terminal, and the second transistor has a second control terminal. In an example, the first and second transistors are configured to split a current at the inductor terminal. The apparatus further includes a controller having first and second control outputs, where the first control output is coupled to the first control terminal, the second control output is coupled to the second control terminal.

Abstract: Described embodiments include a rectifier circuit comprising a first resistor with first and second resistor terminals, and a second resistor with third and fourth resistor terminals. The first and third resistor terminals are coupled to an auxiliary power terminal. A current source is coupled between the second resistor terminal and a ground terminal. An amplifier has a first amplifier input coupled to the second resistor terminal, and a second amplifier input coupled to the fourth resistor terminal. A first transistor is coupled between the fourth resistor terminal and a damping terminal, and has a first control terminal coupled to the first amplifier output. A gate drive circuit has an input coupled to the damping terminal. A second transistor is coupled between the damping terminal and a bootstrap supply terminal, and has a second control terminal coupled to an output of the gate drive circuit.

Abstract: In described examples, an integrated circuit includes first and second current sources, first and second switches, a dV/dt phase detector, a control circuit, and source, gate, and drain terminals for coupling to, respectively, a source, gate, and drain of a power FET. The first switch is coupled between the first current source and the gate terminal. The second switch is coupled between the second current source and the gate terminal. The dV/dt phase detector detects a dV/dt phase of the power FET and outputs to the control circuit. The control circuit controls the first and second switches to perform a turn-on sequence of the power FET, including: closing the first switch while keeping the second switch open; and after receiving a signal from the dV/dt phase detector indicating the dV/dt phase has started, opening the first switch, and closing the second switch.

Abstract: A circuit support structure includes a first metal layer, a second metal layer, isolation material containing the first and second metal layers, an isolation circuit, a first plurality of contact pads, and a second plurality of contact pads. The isolation circuit includes a first circuit element in the first metal layer and a second circuit element in the second metal layer and electrically isolated from the first circuit element by the isolation material. The first plurality of contact pads is adapted to be coupled to a first integrated circuit on the circuit support structure and includes a first contact pad electrically coupled to the first circuit element. The second plurality of contact pads is adapted to be coupled to a second integrated circuit on the circuit support structure and includes a second contact pad electrically coupled to the second circuit element.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.

Abstract: A circuit support structure includes a first metal layer, a second metal layer, isolation material containing the first and second metal layers, an isolation circuit, a first plurality of contact pads, and a second plurality of contact pads. The isolation circuit includes a first circuit element in the first metal layer and a second circuit element in the second metal layer and electrically isolated from the first circuit element by the isolation material. The first plurality of contact pads is adapted to be coupled to a first integrated circuit on the circuit support structure and includes a first contact pad electrically coupled to the first circuit element. The second plurality of contact pads is adapted to be coupled to a second integrated circuit on the circuit support structure and includes a second contact pad electrically coupled to the second circuit element.

Abstract: A startup circuit adapted to be coupled to an input voltage supply and operable to supply an output voltage at an output terminal, the startup circuit including: a first transistor having a first control terminal, a first current terminal and a second current terminal, the first current terminal adapted to be coupled to the input voltage supply and the second current terminal coupled to the output terminal; a precharge circuit having a first terminal, a second terminal and a third terminal, the second terminal adapted to be coupled to the input voltage supply and the third terminal coupled to the first control terminal; a current limiter coupled to the precharge circuit, the first control terminal and the second current terminal; a second transistor having a second control terminal, a third current terminal and a fourth current terminal, the third current terminal coupled to the precharge circuit and the second control terminal adapted to be coupled to a control signal; and a third transistor having a third c

Abstract: Described embodiments include a rectifier circuit comprising a first resistor with first and second resistor terminals, and a second resistor with third and fourth resistor terminals. The first and third resistor terminals are coupled to an auxiliary power terminal. A current source is coupled between the second resistor terminal and a ground terminal. An amplifier has a first amplifier input coupled to the second resistor terminal, and a second amplifier input coupled to the fourth resistor terminal. A first transistor is coupled between the fourth resistor terminal and a damping terminal, and has a first control terminal coupled to the first amplifier output. A gate drive circuit has an input coupled to the damping terminal. A second transistor is coupled between the damping terminal and a bootstrap supply terminal, and has a second control terminal coupled to an output of the gate drive circuit.

Abstract: A depletion-mode current source having a saturation current of sufficient accuracy for use as a pre-charge circuit in a start-up circuit of an AC-to-DC power converter is fabricated using an enhancement-mode-only process. The depletion-mode current source can be fabricated on the same integrated circuit (IC) as a gallium nitride field-effect transistor (FET) and resistive and capacitive components used in the start-up circuit, without affecting the enhancement-mode-only fabrication process by requiring additional masks or materials, as would be required to fabricate a depletion-mode FET on the same IC as an enhancement-mode FET. The current source includes a resistive patterned two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) channel coupled between two terminals and one or more metal field plates extending from one of the terminals and overlying the patterned area of the channel, the field plates being separated from the channel and from each other by dielectric layers.

Abstract: Reference voltage generation circuits and related methods are disclosed. An example reference voltage generation circuit includes a voltage generating circuit including an enhancement mode (E-mode) gallium nitride (GaN) transistor, the voltage generating circuit to, in response to a first clock signal having a first phase, generate a first voltage associated with the E-mode GaN transistor, and, in response to a second clock signal having a second phase different from the first phase, generate a second voltage associated with the E-mode GaN transistor, and a switching capacitor circuit coupled to the voltage generating circuit, the switching capacitor circuit to generate a reference voltage based on a difference between the first voltage and the second voltage.

Abstract: In described examples, a device includes an interconnect substrate that has an aperture through the interconnect substrate. An integrated circuit (IC) die that has an on-chip element is mounted on the interconnect substrate with the on-chip element aligned with and facing the aperture. The IC die is over-molded with mold compound only on one side of the interconnect substrate so that the aperture remains free of mold compound to allow the on-chip element to have access to the environment.