Abstract: An apparatus includes: a package substrate having a first set of leads spaced from a first die pad, and a second set of leads spaced from a second die pad, a space between the first and the second die pad forming an electrical isolation barrier; a bobbin mounted on the second die pad; a first coil around a first portion of the bobbin and coupled to a first semiconductor die on the first die pad, and a second coil around a second portion of the bobbin coupled to a second semiconductor die on the second die pad, the first coil, the second coil and the bobbin forming a micro-transformer; and mold compound covering the first die pad, the second die pad, the micro-transformer, portions of the first set of leads, and portions of the second set of leads, the mold compound forming a body of a microelectronic device package.

Abstract: A depletion-mode current source having a saturation current of sufficient accuracy for use as a pre-charge circuit in a start-up circuit of an AC-to-DC power converter is fabricated using an enhancement-mode-only process. The depletion-mode current source can be fabricated on the same integrated circuit (IC) as a gallium nitride field-effect transistor (FET) and resistive and capacitive components used in the start-up circuit, without affecting the enhancement-mode-only fabrication process by requiring additional masks or materials, as would be required to fabricate a depletion-mode FET on the same IC as an enhancement-mode FET. The current source includes a resistive patterned two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) channel coupled between two terminals and one or more metal field plates extending from one of the terminals and overlying the patterned area of the channel, the field plates being separated from the channel and from each other by dielectric layers.

Abstract: A circuit includes a half-bridge circuit is configured to provide a switching voltage responsive to respective high-side and low-side drive signals. High-side slew control circuitry is configured to provide a high-side slew-compensated control signal responsive to a high-side enable signal and a slew current signal representative of a slew rate at a switching output. A high-side driver is configured to provide the high-side drive signal responsive to the high-side slew-compensated control signal. Low-side slew control circuitry is configured to provide a low-side slew-compensated drive signal responsive to a low-side enable signal and the slew current signal. A low-side driver is configured to provide the low-side drive signal responsive to the low-side slew-compensated control signal. A capacitor is coupled between the high-side and low-side slew control circuitry and is configured to convert the slew rate to the slew current signal.

Abstract: An apparatus includes a power converter that includes a coupled inductor including a primary side terminal and a secondary side terminal, a primary switch coupled to the primary side terminal, and a rectifier switch coupled to the secondary side terminal. The apparatus also includes a primary side controller coupled to the primary switch, and a secondary side controller coupled to the rectifier switch. The primary side controller is configured to transmit a control signal to the secondary side controller via a wireless channel, the control signal indicating an operation mode of a plurality of operation modes of the power converter.

Abstract: A self-biasing circuit for power converters is disclosed. In an example, an apparatus includes a first transistor coupled between an inductor terminal and a ground terminal, and a second transistor coupled between the inductor terminal and a bias terminal. The first transistor has a first control terminal, and the second transistor has a second control terminal. In an example, the first and second transistors are configured to split a current at the inductor terminal. The apparatus further includes a controller having first and second control outputs, where the first control output is coupled to the first control terminal, the second control output is coupled to the second control terminal.

Abstract: Described embodiments include a protection circuit having a voltage attenuator circuit with an input coupled to a switch terminal. A filter circuit has a filter input coupled to the output of the attenuator. A first transistor has a first current terminal coupled to a power supply terminal, and a first control terminal coupled to the filter output. A second transistor, which is matched to the first transistor, has a third current terminal coupled to the first current terminal, a second control terminal coupled to the first control terminal, and a fourth current terminal coupled to a first voltage sense terminal. A buffer circuit has a buffer input coupled to the attenuator output. A S/H circuit has a sample input coupled to the buffer output, and a sample output providing a minimum ringing voltage of a signal from the switch terminal.

Abstract: An example apparatus includes: an AC supply terminal; first current source circuitry having a first terminal, a second terminal, and a control terminal; second current source circuitry having a first terminal and a control terminal, the first terminal of the second current source circuitry coupled to the AC supply terminal and the first terminal of the first current source circuitry; a capacitor having a terminal; comparator circuitry having an input terminal and an output terminal, the input terminal of the comparator circuitry coupled to the terminal of the capacitor and the second terminal of the first current source circuitry; and timer circuitry having an input terminal, a first output terminal, and a second output terminal, the input terminal of the timer circuitry coupled to the output terminal of the comparator circuitry, the first output terminal of the timer circuitry coupled to the control terminal of the first current source circuitry.

Abstract: A circuit includes a first transistor, a second transistor and a controller. The first transistor has a first terminal coupled to a switching terminal, a second terminal coupled to a reference terminal, and a control terminal. The first transistor is a gallium nitride transistor. The second transistor has a first terminal coupled to the switching terminal, a second terminal coupled to the reference terminal, and a control terminal. The controller has a first output coupled to the control terminal of the first transistor, and a second output coupled to the control terminal of the second transistor.

Abstract: A circuit includes a first driver, a second driver, and a bias generator. First driver has a first bias terminal, a first reference terminal, a first driver input, and a first driver output. The second driver has a second bias terminal, a second reference terminal, a second driver input, and a second driver output. The bias generator has a first input, a second input, a first bias output, and a second bias output, the first input coupled to the first reference terminal, the second input coupled to the second reference terminal, the first bias output coupled to the first bias terminal, and the second bias output coupled to the second bias terminal, wherein the bias generator is configurable to generate, based on a supply voltage, a first bias voltage at the first bias output and a second bias voltage at the second bias output.

Abstract: Techniques for valley detection in flyback power converters. In an example, circuitry implementing the techniques is configured to detect a positive slew at the onset of the leakage reset portion of the switching terminal signal, and to blank out the leakage reset portion. The circuitry is also configured to detect a negative slew of the leakage ringing portion of the switching terminal signal, and to blank out any false valley detections that occur during the leakage ringing portion. The blanking periods may be fixed or variable. The circuitry may also be configured to discern the difference between a true valley that reaches zero voltage within the magnetizing ringing portion and a false valley within the leakage ringing portion.

Abstract: Techniques for valley detection in flyback power converters. In an example, circuitry implementing the techniques is configured to generate a first indication of an over-voltage protection (OVP) condition of a flyback power converter, using a switching terminal signal of the flyback power converter. The circuitry is further configured to generate a second indication of an input voltage surge condition of the flyback power converter, using the switching terminal signal of the flyback power converter. The circuitry further is further configured to suppress the first indication, responsive to the second indication being generated.

Abstract: An apparatus includes a switch circuit, first through fourth transistors, and a comparator. The switch circuit has first and second terminals. The first transistor has first and second terminals and a control terminal. The second terminal is coupled to the second terminal of the switch circuit. The second transistor has first and second terminals and a control terminal. The control terminals of the first and second transistors are coupled together. The third transistor has first and second terminals and a control terminal. The fourth transistor has first and second terminals and a control terminal. The control terminals of the third and fourth transistors are coupled together, and the first terminals of the first, second, third, and fourth transistors are coupled together. The comparator has first and second comparator inputs. The first comparator input is coupled to the second terminals of the second and fourth transistors.

Abstract: A packaged integrated circuit (IC) including a semiconductor die having a metallization layer, the metallization layer including first metal interconnects in a first insulation material. The IC includes a first substrate on the metallization layer, the first substrate including second metal interconnects in a second insulation material different from the first insulation material, at least one of the second metal interconnects being electrically coupled to at least one of the first metal interconnects. The IC further includes a second substrate on the first substrate, the second substrate including an isolation circuit and third metal interconnects in a third insulation material different from the first insulation material, the isolation circuit being electrically coupled to the at least one of the first metal interconnects via the at least one of the second metal interconnects and at least one of the third metal interconnects.

Abstract: A self-biasing circuit for power converters is disclosed. In an example, an apparatus includes a first transistor coupled between an inductor terminal and a ground terminal, and a second transistor coupled between the inductor terminal and a bias terminal. The first transistor has a first control terminal, and the second transistor has a second control terminal. In an example, the first and second transistors are configured to split a current at the inductor terminal. The apparatus further includes a controller having first and second control outputs, where the first control output is coupled to the first control terminal, the second control output is coupled to the second control terminal.

Abstract: An apparatus comprising a current source having a current control input and a current source output, the current source output coupled to a first transistor control terminal. The apparatus further comprises a transistor coupled between the first transistor control terminal and a current drain (or sink) terminal, the transistor having a second transistor control terminal. The apparatus further comprises an amplifier having a first input, a second input, and an amplifier output, the first input coupled to the first transistor control terminal, the second input coupled to a reference terminal, and the amplifier output coupled to the current control input and the second transistor control terminal.

Abstract: In one example, an apparatus comprises: a first transistor having a first control terminal and first and second current terminals; a capacitor coupled between a switching terminal and the first current terminal; a second transistor having a second control terminal and coupled between the switching terminal and a ground terminal; and a sensing and control circuit having a power terminal, a third current terminal, an enable input and a transistor control output, the third current terminal coupled to the second current terminal, the enable input coupled to the second control terminal, and the transistor control output coupled to the first control terminal.

Abstract: In examples, an isolation device comprises a multi-level substrate having opposing first and second surfaces. The multi-level substrate includes a first coil in a first layer of the substrate, the first coil having first and second terminals, a second coil in a second layer of the substrate that is vertically distanced from the first layer, the second coil having third and fourth terminals, and a dielectric material covering the first and second coils. The device comprises a first semiconductor die coupled to the first surface and to the first and second terminals, a second semiconductor die coupled to the second surface and to the third and fourth terminals, the second semiconductor die galvanically isolated from the first semiconductor die, conductive terminals coupled to the multi-level substrate, and a mold compound covering the multi-level substrate, the first and second semiconductor dies, and the conductive terminals.

Abstract: Described embodiments include a rectifier circuit comprising a first resistor with first and second resistor terminals, and a second resistor with third and fourth resistor terminals. The first and third resistor terminals are coupled to an auxiliary power terminal. A current source is coupled between the second resistor terminal and a ground terminal. An amplifier has a first amplifier input coupled to the second resistor terminal, and a second amplifier input coupled to the fourth resistor terminal. A first transistor is coupled between the fourth resistor terminal and a damping terminal, and has a first control terminal coupled to the first amplifier output. A gate drive circuit has an input coupled to the damping terminal. A second transistor is coupled between the damping terminal and a bootstrap supply terminal, and has a second control terminal coupled to an output of the gate drive circuit.

Abstract: The present disclosure generally relates to a semiconductor device having a slanted field plate. In an example, a semiconductor device includes a semiconductor substrate, a gate, a drain contact, a source contact, and a field plate. The gate is on a surface of the semiconductor substrate. The drain contact and a source contact are on the semiconductor substrate. The field plate is over the surface of the semiconductor substrate and extends from one side of the gate towards the drain contact. The field plate includes multiple field plate portions. Each of the multiple field plate portions has a uniform respective slope with respect to the surface, and the multiple field plate portions have different slopes.

Abstract: An apparatus includes a first transistor having a first transistor control terminal and coupled between a power terminal and a switching terminal. The apparatus further includes a second transistor having a second transistor control terminal and coupled between the switching terminal and a ground terminal. The apparatus further includes a first switch coupled between the power terminal and the second transistor control terminal, the first switch having a first switch control terminal; The apparatus further includes a second switch coupled between the second control terminal and the ground terminal, the second switch having a second switch control terminal. The apparatus also includes a controller having a control input, a first control output, and a second control output, the control input coupled to the second transistor control terminal, the first control output coupled to the first switch control terminal, and the second control output coupled to the second switch control terminal.