Abstract: The following description pertains to processing substrates using processes such as, but not limited to, polishing or lapping. Descriptions of systems, methods, and apparatuses according to one or more embodiments of the present invention are presented.

Abstract: An aspect of the present invention pertains to a method of fabricating wafers. One embodiment comprises a method of processing a substrate having defects into a wafer. The method comprises grinding the substrate to flatness while supporting the substrate in a grinding apparatus so that there is minimum or substantially zero stress on the substrate. Another aspect of the present invention comprises a substrate holder for holding a substrate as part of grinding processes to produce a flat surface on the substrate.

Abstract: A CMOS integrated circuit structure is disclosed having a patterned nitride passivation layer, wherein the nitride is patterned such that it does not overlie the thin gate oxide portions of one or more of the MOS devices. When protection against the effects of external radiation is desired, the thin gate oxide areas of the PMOS devices are left uncovered by the patterned nitride passivation layer. When protection is desired against the effects of internally generated "hot electrons", the thin gate oxide areas of the NMOS devices are left uncovered by the patterned nitride passivation layer.

Abstract: A technique for improving the radiation hardness and hot-electron resistance of a CMOS integrated circuit is described whereby undesirable hydrogen ions may be vented through any holes, such as contact holes, in an overlying passivation layer by applying an elevated temperature and/or electrical bias to the integrated circuit die. The elevated temperature and electrical bias serve to accelerate the process by which hydrogen vents from the die. The elimination of unwanted hydrogen significantly reduces threshold shifts in the CMOS integrated circuit, providing greater radiation hardness and hot-electron resistance.