Abstract: An adaptive phase-locked loop (PLL) circuit produces an output signal having a frequency in reference to the frequency of a reference signal. The PLL circuit includes an oscillator configured to generate the output signal according to a frequency control signal, and a processing circuit configured to generate a feedback signal deriving from the output signal. An adjustable shift circuit is provided to time-shift the feedback signal. The PLL further includes a phase comparison circuit configured to generate a phase error signal indicating a phase error between the time-shifted feedback signal and the reference signal, and a control circuit configured to generate the frequency control signal based on the phase error signal. The adjustable shift circuit adjusts a time-shift amount to time-shift the feedback signal according to the phase error signal.

Abstract: An adaptive phase-locked loop (PLL) circuit produces an output signal having a frequency in reference to the frequency of a reference signal. The PLL circuit includes an oscillator configured to generate the output signal according to a frequency control signal, and a processing circuit configured to generate a feedback signal deriving from the output signal. An adjustable shift circuit is provided to time-shift the feedback signal. The PLL further includes a phase comparison circuit configured to generate a phase error signal indicating a phase error between the time-shifted feedback signal and the reference signal, and a control circuit configured to generate the frequency control signal based on the phase error signal. The adjustable shift circuit adjusts a time-shift amount to time-shift the feedback signal according to the phase error signal.

Abstract: A multi-bit analog-to-digital converter architecture, which during normal operation behaves like a single-bit converter, thus sharing the high linearity and low distortion properties of the simpler system. When a high input signal is applied, a second bit is triggered and the system behaves like a more complex multi-bit system, providing system stability where a single-bit comparator would overload and the system would become unstable. During normal operation, a single-bit converter is sufficient to stabilize the system. When the input is a large, sustained signal (relative to the full scale of the converter) this single-bit approach is not sufficient to maintain system stability. Thus, if the input to the analog-to-digital converter is close to its maximum or minimum range (implying a large positive or negative input signal) a second bit is triggered, providing stable linearity where the signal-to-noise ratio of a conventional sigma-delta converter would rapidly drop off.