Abstract: A magnet structure particularly suitable for partial human body magnetic resonance imaging. A superconductive magnet assembly consisting of a plurality of axially symmetric low and/or high temperature superconductors through which currents are induced to flow. One or more of the superconductors are at locations close to the region of homogeneous field. Geometry and locations of the superconductors and current through the superconductors are such that a substantially homogenous magnetic field results in a selected region.

Abstract: An imaging system acquires imaged data from a non-invasive examination of the subject. The data is transferred among various image processing agents on a data bus. A data acquisition agent receives the image data from the non-invasive examination and generates subsequent agent locations and transmits the subsequent agent locations and the packets of image data along the data bus. Various image processing agents each receive packets of data transmitted with that agent's location and performs imaging and processing operations on the data packets generating another agent location and thereafter transmitting the other agent location and process data packets along the data bus. The display agent receives the processed image data packets from one of the image processing agents via the data bus, stores the processed image data packets and communicates the process image data to a man-readable image display.

Abstract: A customized random access memory circuit is provided to allow the processing of extremely high amounts of data in an area of very small physical size. The chip contains a group of interconnected registers with a set of input ports and a set of output ports. The input ports have individual write enable signals to allow them to write to selected address locations. A switching circuit is provided to ensure that the proper data from the proper input port goes to the chosen address location. A first and second set of latches are provided where the first set of latches are connected to a multiplexor first and the second set of latches are connected to a second multiplexor. The chip also contains a cycle skipping chip to allow the data to maintain its position and not be transferred through at least one clock cycle. Selected data sets which are going to be outputted have the data internally swapped to prepare it for use in floating point operations.

Abstract: An array processor has been designed in a highly paralleled fashion thereby allowing extremely fast movement of data. Two 32-bit words come out of an internal data memory device. This data is fed into a register file. On the same clock cycle, three 32-bit results are coming out of an arithmetic unit. Those results feed back into the register file. Therefore, on a single clock cycle, five separate pieces of data are going into the register file. In the same clock cycle, other data coming out of the outputs of the register file feed data into two separate floating arithmetic adders and one floating arithmetic multiplier. The design of the present embodiment allows a constant flow of data to be supplied to the arithmetic unit thereby using the arithmetic unit to its maximum functioning ability.

Abstract: An imaging method and apparatus having a new and improved data filter. In one application of the invention computed tomography number inaccuracies are avoided by use of a new filter function derived from discrete points of a truncated spatial domain convolution filter. The points from the truncated convolution filter are fourier transformed to yield a ramp filter with ripple in the spatial frequency domain. Data from a CT scan is filtered with this new filter function and back projected to produce images that do not exhibit CT number inaccuracies.