Abstract: A circuit and method for calibrating a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a VCO and a bias control circuit coupled to a tail node of the VCO. An amplitude control unit may also be coupled to the tail node, wherein the amplitude control unit is configured to determine the amplitude of a VCO output signal based on a voltage present on the tail node. The amplitude control unit may also be configured to generate a bias voltage based on the amplitude of the VCO output signal and a target voltage. The bias control circuit may be coupled to receive the bias voltage from the amplitude control unit and may be further configured to adjust the voltage on the tail node based on the received bias voltage.

Abstract: A circuit and method for calibrating a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a VCO and a bias control circuit coupled to a tail node of the VCO. An amplitude control unit may also be coupled to the tail node, wherein the amplitude control unit is configured to determine the amplitude of a VCO output signal based on a voltage present on the tail node. The amplitude control unit may also be configured to generate a bias voltage based on the amplitude of the VCO output signal and a target voltage. The bias control circuit may be coupled to receive the bias voltage from the amplitude control unit and may be further configured to adjust the voltage on the tail node based on the received bias voltage.

Abstract: A phase-locked loop includes a voltage-controlled oscillator and a charge-pump loop filter. The voltage-controlled oscillator includes a varactor having a first set of capacitor cells configured to adjust a capacitance based on a first control voltage, and a second set of capacitor cells configured to adjust a capacitance based on a second control voltage. The charge-pump loop filter receives a first and a second update signal, each having at least one state based on a phase difference between a first clock and a second clock, and comprises a first component and a second component. The first component is configured to adjust, during an update period, a voltage across an impedance from a reference level based on the states of the first and second update signals and to return the voltage across the impedance to the reference level prior to an end of the update period, wherein the voltage across the impedance comprises the first control voltage.