Abstract: A vector register provides the capability for simultaneously writing through at least two write ports and simultaneously reading from at least two read ports. In addition, a barber pole technique for storing words from logical vector registers into banks is provided to minimize conflicts.

Abstract: The present circuitry operates with a computer system which employs a CPU, memory, and other data handling devices such as peripherals and terminals. All of the foregoing elements of the computer system are connected to a major signal bus. The computer system functions by transmitting data and instructions from one element to another in accordance with a principal protocol. However, the present system does provide for decoding address signals, which are transmitted on the major signal bus, and if such address signals are acceptable to the memory then a new set of timing signals and a new set of protocol control signals are generated. In response to these new timing signals and new protocol control signals, data is transferred between the memory and the CPU at a faster rate and under a different protocol than the principal protocol thereby making the computer system function faster than heretofore.