Abstract: A system and method for transferring files from a source file server in one network domain to a destination file server in a second separate network domain. A first hardware server computer monitors the source file server for the presence of a new manifest file, downloads the new manifest file, downloads each file identified in the new manifest file; and forwards each downloaded file on an output coupled to an input of a one-way link. The one-way link transfers files only from the input to an output thereof and prevents any signal from passing from the output to the input. A second hardware server is connected to the output of the one-way link and receives each file output from the one-way link and forwards each received file to a file location on the destination file server corresponding to an original file location of that file on the source file server.

Abstract: Three embodiments of one-way cross-domain systems for transferring information from a client in a first security domain to a server in a second separate security domain are disclosed. In addition, three embodiments of bilateral cross-domain systems for transferring first information from a client in a first security domain to a server in a second separate security domain and second information from the server in the second separate security domain to the client in the first security domain are also disclosed. Each of the one-way and bilateral cross-domain systems is based upon a single computer server which employs a number of virtual machines to implement send and receive servers. The single computer server also implements one (for the one-way cross-domain systems) or two (for the bilateral cross-domain systems) virtual one-way data links in either virtual machines or within the hypervisor portion of the operating system.

Abstract: Three embodiments of one-way cross-domain systems for transferring information from a client in a first security domain to a server in a second separate security domain are disclosed. In addition, three embodiments of bilateral cross-domain systems for transferring first information from a client in a first security domain to a server in a second separate security domain and second information from the server in the second separate security domain to the client in the first security domain are also disclosed. Each of the one-way and bilateral cross-domain systems is based upon a single computer server which employs a number of virtual machines to implement send and receive servers. The single computer server also implements one (for the one-way cross-domain systems) or two (for the bilateral cross-domain systems) virtual one-way data links in either virtual machines or within the hypervisor portion of the operating system.

Abstract: A method for mirroring data between virtual machines includes intercepting a write command initiated from a virtual machine. Address and data information from the intercepted write command is stored within a queue located within a memory buffer of the primary server. The stored address and data information is transferred, upon filling the queue of the memory buffer of the primary server to a predetermined level, to a dedicated region of the memory of the primary server. The stored address and data information is sent from the dedicated region of the memory of the primary server to a backup server upon filling of the dedicated region of the memory of the primary server to a predetermined level.

Abstract: A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. When two translation table entries reference identical fragments in a memory block, one of the translation table entries is changed to refer to the same memory block referenced in the other translation table entry, which frees up a memory block. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries. When a translation table has a private delta, its delta bit is set.

Abstract: A method for mirroring data between virtual machines includes intercepting a write command initiated from a virtual machine. Address and data information from the intercepted write command is stored within a queue located within a memory buffer of the primary server. The stored address and data information is transferred, upon filling the queue of the memory buffer of the primary server to a predetermined level, to a dedicated region of the memory of the primary server. The stored address and data information is sent from the dedicated region of the memory of the primary server to a backup server upon filling of the dedicated region of the memory of the primary server to a predetermined level.

Abstract: A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. When two translation table entries reference identical fragments in a memory block, one of the translation table entries is changed to refer to the same memory block referenced in the other translation table entry, which frees up a memory block. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries. When a translation table has a private delta, its delta bit is set.

Abstract: A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. When two translation table entries reference identical fragments in a memory block, one of the translation table entries is changed to refer to the same memory block referenced in the other translation table entry, which frees up a memory block. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries. When a translation table has a private delta, its delta bit is set.

Abstract: A method and circuit for implementing a cache directory and efficient cache tag lookup in very large cache systems, and a design structure on which the subject circuit resides are provided. A tag cache includes a fast partial large (LX) cache directory maintained separately on chip apart from a main LX cache directory (LXDIR) stored off chip in dynamic random access memory (DRAM) with large cache data (LXDATA). The tag cache stores most frequently accessed LXDIR tags. The tag cache contains predefined information enabling access to LXDATA directly on tag cache hit with matching address and data present in the LX cache. Only on tag cache misses the LXDIR is accessed to reach LXDATA.

Abstract: A method for detecting errors in a tag array includes accessing the tag array with an index, retrieving at least one tag from the tag array, and computing a parity bit based on the expected tag.

Abstract: We describe, in exemplary embodiments, an on-chip Functional Built-In Self Test (“FBIST”) mechanism for testing integrated circuits with internal memory state and complex transaction based interfaces. Such interfaces include system-on-chip applications, memory chip applications, and input/output (“IO”) protocol adapter chips.

Abstract: A method for detecting errors in a tag array includes accessing the tag array with an index, retrieving at least one tag from the tag array, and computing a parity bit based on the expected tag.

Abstract: A method for sending and receiving asynchronous signals using optical techniques. The present invention implements open-drain circuit signaling utilizing a Finite State Machine and additional logic to reduce power requirements when transmitting asynchronous information via an optical transmission line. An embodiment exploits the 8 bit/10 bit encoder to detect errors and signal the beginning of valid data along the transmission line. The asynchronous signals may be transmitted during transitions in the Finite State Machine.

Abstract: This invention is a high performance, standard IO interconnect "bridge" hardware for a parallel machine with a packet switching network in place. Combining new hardware and new software, this bridge connects parallel processors to the external world. The hardware is a "bridge" connecting an internal inter-processor switch to external asynchronous transfer node networks. The software is a "mirror" for making the connections. The invention provides high bandwidth, low latency and deterministic performance, and is inexpensive to build.