Abstract: A polymeric substrate is disclosed. The polymeric substrate comprises a barrier layer including a polymeric material comprising about 50 wt. % or more of at least one polyolefin polymer and 50 wt. % or less of a hydrocarbon resin. The polymeric material exhibits a DTUL of 30° C. or more and a tensile modulus of 500 MPa or more and/or a flexural secant modulus of 500 MPa or more. The barrier layer has a thickness of greater than 200 ?m to 6,500 ?m. A shaped polymeric article comprising the polymeric substrate is also disclosed.

Abstract: A polymeric substrate is disclosed. The polymeric substrate comprises a barrier layer including a polymeric material comprising about 50 wt. % or more of at least one polyolefin polymer and 50 wt. % or less of a hydrocarbon resin. The polymeric material exhibits a DTUL of 30° C. or more and a tensile modulus of 500 MPa or more and/or a flexural secant modulus of 500 MPa or more. The barrier layer has a thickness of greater than 200 ?m to 6,500 ?m. A shaped polymeric article comprising the polymeric substrate is also disclosed.

Abstract: A polymeric substrate is disclosed. The polymeric substrate comprises a barrier layer including a polymeric material comprising about 50 wt. % or more of at least one polyolefin polymer and 50 wt. % or less of a hydrocarbon resin. The polymeric material exhibits a DTUL of 30° C. or more and a tensile modulus of 500 MPa or more and/or a flexural secant modulus of 500 MPa or more. The barrier layer has a thickness of greater than 200 ?m to 6,500 ?m. A shaped polymeric article comprising the polymeric substrate is also disclosed.

Abstract: A polymeric substrate is disclosed. The polymeric substrate comprises a barrier layer including a polymeric material comprising about 50 wt. % or more of at least one polyolefin polymer and 50 wt. % or less of a hydrocarbon resin. The polymeric material exhibits a DTUL of 30° C. or more and a tensile modulus of 500 MPa or more and/or a flexural secant modulus of 500 MPa or more. The barrier layer has a thickness of greater than 200 ?m to 6,500 ?m. A shaped polymeric article comprising the polymeric substrate is also disclosed.

Abstract: A polymeric substrate is disclosed. The polymeric substrate comprises a barrier layer including a polymeric material comprising about 50 wt. % or more of at least one polyolefin polymer and 50 wt. % or less of a hydrocarbon resin. The polymeric material exhibits a DTUL of 30° C. or more and a tensile modulus of 500 MPa or more and/or a flexural secant modulus of 500 MPa or more. The barrier layer has a thickness of greater than 200 ?m to 6,500 ?m. A shaped polymeric article comprising the polymeric substrate is also disclosed.

Abstract: The invention relates to a live vaccine for protection against enteric bacterial infection.

Abstract: An arithmetic logic stage in a graphics pipeline includes a number of arithmetic logic units (ALUs). The ALUs each include, for example, a multiplier and an adder. The ALUs are interconnected by circuitry that, for example, routes the output from the multiplier in one ALU to both the adder in that ALU and an adder in another ALU.

Abstract: An efficient pipeline debug statistics system and method are described. In one embodiment, an efficient pipeline debug is utilized in a graphics processing pipeline of a handheld device. In one embodiment, a pipeline debug statistics system includes a plurality of pipeline stages with probe points, a central statistic component, and a debug control component. The plurality of pipeline stages with probe points perform pipeline operations. The central statistic block gathers information from the probe points. The debug control component directs the gathering of information from the probe points. In one exemplary implementation, debug control component can direct gathering of information at a variety of levels and abstraction.

Abstract: Techniques for providing a heads-down display on a wireless device are described. An environmental signal representing actual images may be received from one or more cameras associated with the wireless device. The actual images may be of a physical environment in proximity to a current location of the wireless device. An application signal, representing application renderings associated with an application currently executing at the wireless device, may be received. The actual images and the application renderings may be simultaneously rendered on a screen associated with the wireless device. The actual images and the application renderings may be rendered as ordered layers on the screen.

Abstract: A method for loading a shader program from system memory into GPU memory. The method includes accessing the shader program in system memory of a computer system. A DMA transfer of the shader program from system memory into GPU memory is performed such that the shader program is loaded into GPU memory in an address independent manner.

Abstract: Data for data elements (e.g., pixels) can be stored in an addressable storage unit that can store a number of bits that is not a whole number multiple of the number of bits of data per data element. Similarly, a number of the data elements can be transferred per unit of time over a bus, where the width of the bus is not a whole number multiple of the number of bits of data per data element. Data for none of the data elements is stored in more than one of the storage units or transferred in more than one unit of time. Also, data for multiple data elements is packaged contiguously in the storage unit or across the width of the bus.

Abstract: Detailed herein are approaches to enabling conditional execution of instructions in a graphics pipeline. In one embodiment, a method of conditional execution controller operation is detailed. The method involves configuring the conditional execution controller to evaluate conditional test. A pixel data packet is received into the conditional execution controller, and evaluated, with reference to the conditional test. A conditional execution flag, associated with the pixel data packet, is set, to indicate whether a conditional operation should be performed on the pixel data packet.

Abstract: Embodiments for programming a graphics pipeline, and modules within the graphics pipeline, are detailed herein. One embodiment described a method of implementing software assisted shader merging for a graphics pipeline. The method involves accessing a first shader program in memory, and generating a first shader instruction from that program. This first instruction is loaded into an instruction table at a first location, indicated by an offset register. A second shader program in memory is then accessed, and used to generate a second shader instruction. The second shader instruction is loaded into the instruction table at a second location indicated by the offset register.

Abstract: A method for loading and executing an indeterminate length shader program. The method includes accessing a first portion of a shader program in graphics memory of a GPU and loading instructions from the first portion into a plurality of stages of the GPU to configure the GPU for program execution. A group of pixels is then processed in accordance with the instructions from the first portion. A second portion of the shader program is accessed in graphics memory of the GPU and instructions from the second portion are loaded into the plurality of stages of the GPU to configure the GPU for program execution. The group of pixels are then processed in accordance with the instructions from the second portion.

Abstract: An arithmetic logic stage in a graphics pipeline includes a number of arithmetic logic units (ALUs). The ALUs each include, for example, a multiplier and an adder. The ALUs are interconnected by circuitry that, for example, routes the output from the multiplier in one ALU to both the adder in that ALU and an adder in another ALU.

Abstract: Embodiments for programming a graphics pipeline, and modules within the graphics pipeline, are detailed herein. Several of these embodiments utilize offset registers associated with the instruction tables for the modules within the pipeline. The offset register serves as a pointer to locations in the instruction table, which allows instructions to be written to be instruction table, without requiring that the shader programs have explicit addresses. One embodiment describes a method of programming a graphics pipeline. This method involves accessing the shader program stored in memory. A shader instruction is generated from this shader program, and loaded into an instruction table associated with a target module graphics pipeline. The shader instruction is loaded into the instruction table at the location indicated by an offset register.

Abstract: A method of allocating the risk and reward of financial performance that is contingent upon the outcome of sporting events. The business and a second party enter into a contract under which the second party guarantees all or a portion of certain profits to the business that are otherwise contingent upon the sporting event outcome, in exchange for a fee.

Abstract: Data for data elements (e.g., pixels) can be stored in an addressable storage unit that can store a number of bits that is not a whole number multiple of the number of bits of data per data element. Similarly, a number of the data elements can be transferred per unit of time over a bus, where the width of the bus is not a whole number multiple of the number of bits of data per data element. Data for none of the data elements is stored in more than one of the storage units or transferred in more than one unit of time. Also, data for multiple data elements is packaged contiguously in the storage unit or across the width of the bus.

Abstract: A system for invoking a service includes an invoking entity and a network entity such as a service provider. The invoking entity can send a service invocation request to effectuate invocation of a service. The service invocation request is formatted and sent in accordance with a given messaging architecture (e.g., SOAP). The network entity is capable of receiving the service invocation request, such as to invoke the requested service. The network entity can also send a response to the service invocation request, although the response is sent across a SIP architecture. Similar to the service invocation request, the response includes a payload formatted in accordance with the given messaging architecture. Thus, although the network entity can send a response across a SIP architecture, the invoking entity sends the service invocation request independent of the SIP architecture.

Abstract: A system for invoking a service includes an invoking entity and a network entity such as a service provider. The invoking entity can send a service invocation request to effectuate invocation of a service. The service invocation request is formatted and sent in accordance with a given messaging architecture (e.g., SOAP). The network entity is capable of receiving the service invocation request, such as to invoke the requested service. The network entity can also send a response to the service invocation request, although the response is sent across a SIP architecture. Similar to the service invocation request, the response includes a payload formatted in accordance with the given messaging architecture. Thus, although the network entity can send a response across a SIP architecture, the invoking entity sends the service invocation request independent of the SIP architecture.