Abstract: This invention concerns a tubular element for a gas pressure vessel of an airbag module, in particular of a vehicle, wherein the tubular element (1) consists of high-strength steel, has a first and a second end (17, 18) and from the first end (17) to the second end (18) the tubular element (1) has an undeformed section (11), a transition section (12) and a tapering section (13) and on the tapering section (13) at least one radially outwardly extending collar (14) is formed, characterized in that the collar (14) is separated from the transition section (12) by a first length section (130) having an outer diameter (A1) smaller than the outer diameter (A2) of the collar (14) and the wall thickness of the collar (14) is greater than the wall thickness of the first length section (130). Furthermore, the invention concerns a gas pressure vessel and a process for manufacturing a tubular element according to the invention (1).

Abstract: An inner diameter of a first end of a tubular component, positioned in relation to a first die, is reduced through relative movement between the tubular component and the first die such as to produce a first conical area between first and second ends of the tubular component. The first conical area is then formed through relative movement of a second die to create in a longitudinal section of the first conical area an outer circumferential embossment and an inner bead having an inner diameter smaller than the inner diameter of the first end. The first end is widened through insertion of an inner tool, while the tubular component is supported on an outside in a mold cavity of an outer tool. An inner contour with an internal stop is formed as an outer surface of the first end of the tubular component rests flatly in the mold cavity.

Abstract: An inner diameter of a first end of a tubular component, positioned in relation to a first die, is reduced through relative movement between the tubular component and the first die such as to produce a first conical area between first and second ends of the tubular component. The first conical area is then formed through relative movement of a second die to create in a longitudinal section of the first conical area an outer circumferential embossment and an inner bead having an inner diameter smaller than the inner diameter of the first end. The first end is widened through insertion of an inner tool, while the tubular component is supported on an outside in a mold cavity of an outer tool. An inner contour with an internal stop is formed as an outer surface of the first end of the tubular component rests flatly in the mold cavity.

Abstract: This invention concerns a tubular element for a gas pressure vessel of an airbag module, in particular of a vehicle, wherein the tubular element (1) consists of high-strength steel, has a first and a second end (17, 18) and from the first end (17) to the second end (18) the tubular element (1) has an undeformed section (11), a transition section (12) and a tapering section (13) and on the tapering section (13) at least one radially outwardly extending collar (14) is formed, characterized in that the collar (14) is separated from the transition section (12) by a first length section (130) having an outer diameter (A1) smaller than the outer diameter (A2) of the collar (14) and the wall thickness of the collar (14) is greater than the wall thickness of the first length section (130). Furthermore, the invention concerns a gas pressure vessel and a process for manufacturing a tubular element according to the invention (1).

Abstract: The present invention relates to an If blocker or a pharmaceutically acceptable salt thereof for the treatment and/or prevention of a canine patient suffering from heart diseases, preferably heart diseases such as dilated cardiomyopathy (DCM), mitral valve insufficiency (MI), arrthymias, preferably tachyarrthymias, preferably arterial arrhythmias, atrioventricular nodal arrhythmias and/or tachycardia. Each of these diseases may or may not result in heart failure (HF) in canine patients. The invention also relates to improving the quality of life, improving the general health condition as well as a prolonging the life expectancy in canine patients suffering from heart diseases and/or heart failure due to one or more of the following etiologies dilated cardiomyopathy (DCM), mitral valve insufficiency (MI), arrthymias, preferably tachyarrthymias, preferably arterial arrhythmias, atrioventricular nodal arrhythmias and/or tachycardia.

Abstract: A radiation imaging system includes a radiation detector for detecting radiation emitted from a radiation generator; a quick-connect unit configured to activate the radiation generator to initiate radiation emission and to activate the radiation detector to initiate detection of the radiation; and a notification unit included within the quick-connect unit that is configured to notify an operator of a time when the radiation detector is ready to detect the radiation. The quick-connect unit is connectable to the radiation detector and the radiation generator without having to make hardware modifications therein. In an alternate embodiment, the quick-connect unit is a handswitch to be held by an operator, where the notification unit notifies the operator that the radiation detector is ready to detect the radiation, by emitting at least one of a visual signal, a tactile signal and an audible signal.

Abstract: A memory chip with a plurality of FB DRAM cells, having a word line coupled to a first FB DRAM cell and a second FB DRAM cell is disclosed. The memory chip further has a first bit line coupled to the first FB DRAM cell, and a first state memory circuit coupled to the first bit line. The memory chip further includes a second bit line coupled to the second FB DRAM cell, and a second state memory circuit coupled to the second bit line. The memory chip further includes a sense amplifier, which can be coupled to the first FB DRAM cell, the second FB DRAM cell, the first state memory circuit or the second state memory circuit.

Abstract: An integrated circuit having a resistance-based or resistively switching memory cell, and a method for operating a resistively switching memory cell is disclosed. One embodiment is adapted to be put in a low-resistance state by applying a first threshold voltage and in a high-resistance state by applying a second threshold voltage, wherein reading out of the data content from the memory cell is performed by applying a voltage to the memory cell in the range of the first or second threshold voltage or a higher voltage.

Abstract: A memory chip with a plurality of FB DRAM cells, having a word line coupled to a first FB DRAM cell and a second FB DRAM cell is disclosed. The memory chip further has a first bit line coupled to the first FB DRAM cell, and a first state memory circuit coupled to the first bit line. The memory chip further includes a second bit line coupled to the second FB DRAM cell, and a second state memory circuit coupled to the second bit line. The memory chip further includes a sense amplifier, which can be coupled to the first FB DRAM cell, the second FB DRAM cell, the first state memory circuit or the second state memory circuit.

Abstract: According to one embodiment of the present invention, a memory device includes a plurality of resistivity changing memory cells including a current path input terminal and a current path output terminal, respectively, and a plurality of select devices. Each current path output terminal is connected to at least one different current path output terminal via at least one select device.

Abstract: An integrated circuit having a resistance-based or resistively switching memory cell, and a method for operating a resistively switching memory cell is disclosed. One embodiment is adapted to be put in a low-resistance state by applying a first threshold voltage and in a high-resistance state by applying a second threshold voltage, wherein reading out of the data content from the memory cell is performed by applying a voltage to the memory cell in the range of the first or second threshold voltage or a higher voltage.

Abstract: An integrated circuit having a memory array and a method for reducing sneak current in a memory array is disclosed. One embodiment provides a memory array including a plurality of storage devices arranged as a plurality of rows and a plurality of columns. A first voltage is applied to a particular word line to select a column of storage devices. A second voltage is applied to a particular bit line of the plurality of bit lines to select a row of storage devices, and the second voltage is applied to each of further lines except for a further line being connected to the storage devices of the selected column.

Abstract: An integrated circuit having a resistive memory including a resistive memory element, a selection device, a conductive line, and a reference electrode is disclosed. In one embodiment, the conductive line is set to a first voltage for establishing a first resistive state of the resistive memory element and to a second voltage, being lower than the first voltage, for establishing a second resistive state of the resistive memory element. The reference electrode is coupled to the resistive memory element and is set to a voltage level being provided between the first voltage and the second voltage.

Abstract: A memory circuit comprises a plurality of parallel bit-lines connected to a plurality of memory cells, a plurality of sense amplifiers connected to the bit-lines and a plurality of switches each of which being connected to a respective pair of bit-lines out of the plurality of bit-lines for switchably short-circuiting the respective pair of bit-lines. The bit-lines of the respective pair of bit-lines are connected to two different sense amplifiers, and the bit-lines of the respective pair of bit-lines are adjacent to a further bit-line disposed between the bit-lines of the respective pair of bit-lines.

Abstract: A memory device comprises a memory cell array comprising a plurality of memory cells, bitlines being electrically connected to the memory cells of the memory cell array, amplifier circuits being electrically connected to the bitlines and amplifying electrical signals carried in the bitlines, the amplifier circuits being activated and deactivated by means of amplifier circuit control nodes, and at least one potential supplying unit, by means of which potentials can be supplied to the amplifier circuits such that, in the deactivated state of the amplifier circuits, a decrease or a prevention of leakage currents through the amplifier circuits is caused.

Abstract: A portable X-Ray system that includes a first module with an x-ray processor, an input, a monitor, a power supply, an exterior interface, and a sensor panel, the sensor panel being operatively connected in data transfer communication with the x-ray processor by a first connector. The first connector permits the sensor panel to be disposed in spaced apart adjustable position relative to the x-ray processor and a subject to be x-rayed. The first module can be adjusted into a portable stored configuration and an operative configuration, and further includes a shock absorbent element structured to protect the sensor panel, the x-ray processor and the monitor from impacts when in the stored configuration. The system further includes a second module having an x-ray generator that can be disposed between a stored configuration and an operative configuration. A shock absorbent element is provided in the second module to protect the x-ray generator from impacts when the second module is in the stored configuration.

Abstract: The invention relates to a procedure for operating a bus system, as well as a bus system with a line, and two adjoining lines, whereby the lines each comprise two line sections, which are connected with one another by means of a line amplifier and/or buffer device, and whereby the line amplifier and/or buffer device connected with the line sections of the line is constructed as an inverting line amplifier and/or buffer device, and the line amplifier and/or buffer devices connected with the line sections of the adjoining lines are constructed as non-inverting line amplifier and/or buffer devices, or vice versa.

Abstract: An integrated memory has row lines, column lines and column selection lines for activating read/write amplifiers. In each case, one group of a predetermined number of memory cells belongs to a row and a column address. Furthermore, the memory has a number of connecting pads corresponding to the predetermined number. Each memory cell in a group of memory cells is associated with one of the connecting pads. A control circuit for controlling the memory access is designed and can be operated such that, with a column address, it activates at least two different column selection lines. One of the column selection lines is activated for two or more column addresses. The delay times and the line lengths on the memory chip can thus be reduced in size.

Abstract: Integrated circuits, in particular memory chips of the DDR SDRAM type, are tested in a parallel manner. In order to prevent the circuits from being driven relative to one another during a test operation, an input terminal that is already connected to a channel of an automatic test machine anyway is connected to a switching device, by which the output drivers can be turned off in a manner dependent on the control signal that can be fed in at the input terminal. The switching device preferably contains a demultiplexer and also a multiplexer. The demultiplexer can be driven by a test control signal that is additionally generated besides the test control signal. The input terminal is connected to a tester channel anyway during test operation, with the result that no additional external outlay arises.

Abstract: An integrated memory has row lines, column lines and column selection lines for activating read/write amplifiers. In each case, one group of a predetermined number of memory cells belongs to a row and a column address. Furthermore, the memory has a number of connecting pads corresponding to the predetermined number. Each memory cell in a group of memory cells is associated with one of the connecting pads. A control circuit for controlling the memory access is designed and can be operated such that, with a column address, it activates at least two different column selection lines. One of the column selection lines is activated for two or more column addresses. The delay times and the line lengths on the memory chip can thus be reduced in size.