Abstract: A phase generator includes a delay element configured to receive an input signal and delay the input signal by a predetermined amount to develop a delayed version of the input signal, a logic element configured to receive the input signal and the delayed version of the input signal, the logic element configured to produce a signal dependent on a phase difference between the input signal and the delayed version of the input signal, a circuit configured to generate a reference signal, and a comparator configured to receive an output of the logic element and the reference signal. The comparator is configured to generate a control signal that is dependent on the difference between the output of the logic element and the reference signal, where the control signal is applied to the delay element to determine the delay applied to the input signal.

Abstract: An internal loop-back architecture for a parallel serializer/deserializer (SERDES) includes a transmitter macro including a plurality of transmit elements arranged in a parallel architecture, and a receiver macro including a plurality of receive elements arranged in a parallel architecture, wherein at least a portion of the transmit elements and a portion of the receive elements share a communication channel and wherein any of the plurality of transmit elements in a row can communicate with any of the plurality of receive elements in a row, and wherein each of the plurality of transmit element includes a loop-back arrangement with each of the plurality of receive elements.

Abstract: An internal loop-back architecture for a parallel serializer/deserializer (SERDES) includes a transmitter macro including a plurality of transmit elements arranged in a parallel architecture, and a receiver macro including a plurality of receive elements arranged in a parallel architecture, wherein at least a portion of the transmit elements and a portion of the receive elements share a communication channel and wherein any of the plurality of transmit elements in a row can communicate with any of the plurality of receive elements in a row, and wherein each of the plurality of transmit element includes a loop-back arrangement with each of the plurality of receive elements.

Abstract: A system for equalizing transition density in an integrated circuit includes a first circuit configured to transition according to a data stream; and a second circuit configured to transition at a time when the first circuit is not transitioning.

Abstract: A variable delay element includes first and second input stages, each input stage comprising a charge pumping circuit and a discharging circuit, each charge pumping circuit and each discharging circuit associated with the first and second input stages configured to operate on opposite phases of an input signal, and an output stage comprising at least two transistors. The transistors are independently controlled by the first and second input stages and produce an output signal which is a delayed version of the input signal.

Abstract: A system for equalizing transition density in an integrated circuit includes a first circuit configured to transition according to a data stream; and a second circuit configured to transition at a time when the first circuit is not transitioning.

Abstract: A variable delay element includes first and second input stages, each input stage comprising a charge pumping circuit and a discharging circuit, each charge pumping circuit and each discharging circuit associated with the first and second input stages configured to operate on opposite phases of an input signal, and an output stage comprising at least two transistors. The transistors are independently controlled by the first and second input stages and produce an output signal which is a delayed version of the input signal.

Abstract: A phase generator includes a delay element configured to receive an input signal and delay the input signal by a predetermined amount to develop a delayed version of the input signal, a logic element configured to receive the input signal and the delayed version of the input signal, the logic element configured to produce a signal dependent on a phase difference between the input signal and the delayed version of the input signal, a circuit configured to generate a reference signal, and a comparator configured to receive an output of the logic element and the reference signal. The comparator is configured to generate a control signal that is dependent on the difference between the output of the logic element and the reference signal, where the control signal is applied to the delay element to determine the delay applied to the input signal.