Patents by Inventor Michael Mazzola

Michael Mazzola has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8928074
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: January 6, 2015
    Assignee: Power Integrations, Inc.
    Inventors: Lin Cheng, Michael Mazzola
  • Publication number: 20140029152
    Abstract: A fast acting unidirectional or bidirectional electronic circuit breaker for isolating a load from a power-supply unit is described. The described control method for an electronic circuit breaker is capable of instantaneous trip during a short circuit event by improved means of current sensing. The improved control method eliminates the need for additional series components in the conduction path which can add to the circuit breaker's insertion losses. Also, any delay or bandwidth limitations commonly associated with magnetic or hall-effect current sensing methods are eliminated. Circuit breakers with automatic or manual reset options are also described.
    Type: Application
    Filed: March 30, 2012
    Publication date: January 30, 2014
    Applicant: SEMISOUTH LABORATORIES, INC.
    Inventors: Michael MAZZOLA, Robin KELLEY
  • Publication number: 20120187421
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.
    Type: Application
    Filed: March 30, 2012
    Publication date: July 26, 2012
    Applicant: SEMISOUTH LABORATORIES, INC.
    Inventors: Lin CHENG, Michael MAZZOLA
  • Patent number: 8169022
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: May 1, 2012
    Assignee: SS SC IP, LLC
    Inventors: Lin Cheng, Michael Mazzola
  • Publication number: 20100320476
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.
    Type: Application
    Filed: June 18, 2010
    Publication date: December 23, 2010
    Applicant: SemiSouth Laboratories, Inc.
    Inventors: Lin CHENG, Michael MAZZOLA
  • Patent number: 7432171
    Abstract: A silicon carbide semi-insulating epitaxy layer is used to create power devices and integrated circuits having significant performance advantages over conventional devices. A silicon carbide semi-insulating layer is formed on a substrate, such as a conducting substrate, and one or more semiconducting devices are formed on the silicon carbide semi-insulating layer. The silicon carbide semi-insulating layer, which includes, for example, 4H or 6H silicon carbide, is formed using a compensating material, the compensating material being selected depending on preferred characteristics for the semi-insulating layer. The compensating material includes, for example, boron, vanadium, chromium, or germanium. Use of a silicon carbide semi-insulating layer provides insulating advantages and improved thermal performance for high power and high frequency semiconductor applications.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: October 7, 2008
    Assignee: Mississippi State University Research and Technology Corporation (RTC)
    Inventors: Jeffrey B. Casady, Michael Mazzola
  • Publication number: 20080003731
    Abstract: A switching element combining a self-aligned, vertical junction field effect transistor with etched-implanted gate and an integrated antiparallel Schottky barrier diode is described. The anode of the diode is connected to the source of the transistor at the device level in order to reduce losses due to stray inductances. The SiC surface in the SBD anode region is conditioned through dry etching to achieve a low Schottky barrier height so as to reduce power losses associated with the turn on voltage of the SBD.
    Type: Application
    Filed: June 12, 2007
    Publication date: January 3, 2008
    Inventors: Michael Mazzola, Joseph Merrett
  • Publication number: 20070228505
    Abstract: A junction barrier Schottky (JBS) rectifier device and a method of making the device are described. The device comprises an epitaxially grown first n-type drift layer and p-type regions forming p+-n junctions and self-planarizing epitaxially over-grown second n-type drift regions between and, optionally, on top of the p-type regions. The device may include an edge termination structure such as an exposed or buried P+ guard ring, a regrown or implanted junction termination extension (JTE) region, or a “deep” mesa etched down to the substrate. The Schottky contact to the second n-type drift region and the ohmic contact to the p-type region together serve as an anode. The cathode can be formed by ohmic contact to the n-type region on the backside of the wafer. The devices can be used in monolithic digital, analog, and microwave integrated circuits.
    Type: Application
    Filed: April 4, 2006
    Publication date: October 4, 2007
    Inventors: Michael Mazzola, Lin Cheng
  • Publication number: 20070029573
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be implemented in SiC and can include epitaxially grown n-type drift and p-type trenched gate regions, and an n-type epitaxially regrown channel region on top of the trenched p-gate regions. A source region can be epitaxially regrown on top of the channel region or selectively implanted into the channel region. Ohmic contacts to the source, gate and drain regions can then be formed. The devices can include edge termination structures such as guard rings, junction termination extensions (JTE), or other suitable p-n blocking structures. The devices can be fabricated with different threshold voltages, and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used as discrete power transistors and in digital, analog, and monolithic microwave integrated circuits.
    Type: Application
    Filed: August 8, 2005
    Publication date: February 8, 2007
    Inventors: Lin Cheng, Michael Mazzola
  • Publication number: 20060160316
    Abstract: A silicon carbide semi-insulating epitaxy layer is used to create power devices and integrated circuits having significant performance advantages over conventional devices. A silicon carbide semi-insulating layer is formed on a substrate, such as a conducting substrate, and one or more semiconducting devices are formed on the silicon carbide semi-insulating layer. The silicon carbide semi-insulating layer, which includes, for example, 4H or 6H silicon carbide, is formed using a compensating material, the compensating material being selected depending on preferred characteristics for the semi-insulating layer. The compensating material includes, for example, boron, vanadium, chromium, or germanium. Use of a silicon carbide semi-insulating layer provides insulating advantages and improved thermal performance for high power and high frequency semiconductor applications.
    Type: Application
    Filed: December 19, 2005
    Publication date: July 20, 2006
    Inventors: Jeffrey Casady, Michael Mazzola
  • Patent number: 7009209
    Abstract: A silicon carbide semi-insulating epitaxy layer is used to create power devices and integrated circuits having significant performance advantages over conventional devices. A silicon carbide semi-insulating layer is formed on a substrate, such as a conducting substrate, and one or more semiconducting devices are formed on the silicon carbide semi-insulating layer. The silicon carbide semi-insulating layer, which includes, for example, 4H or 6H silicon carbide, is formed using a compensating material, the compensating material being selected depending on preferred characteristics for the semi-insulating layer. The compensating material includes, for example, boron, vanadium, chromium, or germanium. Use of a silicon carbide semi-insulating layer provides insulating advantages and improved thermal performance for high power and high frequency semiconductor applications.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: March 7, 2006
    Assignee: Mississippi State University Research and Technology Corporation (RTC)
    Inventors: Jeffrey B. Casady, Michael Mazzola
  • Publication number: 20060011924
    Abstract: A switching element combining a self-aligned, vertical junction field effect transistor with etched-implanted gate and an integrated antiparallel Schottky barrier diode is described. The anode of the diode is connected to the source of the transistor at the device level in order to reduce losses due to stray inductances. The SiC surface in the SBD anode region is conditioned through dry etching to achieve a low Schottky barrier height so as to reduce power losses associated with the turn on voltage of the SBD.
    Type: Application
    Filed: July 8, 2005
    Publication date: January 19, 2006
    Inventors: Michael Mazzola, Joseph Merrett
  • Publication number: 20020149021
    Abstract: A silicon carbide semi-insulating epitaxy layer is used to create power devices and integrated circuits having significant performance advantages over conventional devices. A silicon carbide semi-insulating layer is formed on a substrate, such as a conducting substrate, and one or more semiconducting devices are formed on the silicon carbide semi-insulating layer. The silicon carbide semi-insulating layer, which includes, for example, 4H or 6H silicon carbide, is formed using a compensating material, the compensating material being selected depending on preferred characteristics for the semi-insulating layer. The compensating material includes, for example, boron, vanadium, chromium, or germanium. Use of a silicon carbide semi-insulating layer provides insulating advantages and improved thermal performance for high power and high frequency semiconductor applications.
    Type: Application
    Filed: January 3, 2002
    Publication date: October 17, 2002
    Inventors: Jeffrey B. Casady, Michael Mazzola
  • Patent number: 6119406
    Abstract: An automotive door trim panel assembly including a plastic inner panel having a relatively thick, rigid, hollow retaining section which is designed for snap-fit installation of the assembly with a weather seal having a snap-on groove defined therein to thereby eliminate the need for additional fastening hardware while at the same time to provide increased rigidity and ease of tooling. The assembly also includes a contour door trim member for the inner panel.
    Type: Grant
    Filed: December 16, 1998
    Date of Patent: September 19, 2000
    Assignee: Patent Holding Company
    Inventors: Salvatore J. Gulisano, Michael Mazzola, Stephen C. Ivy, Rhys Johnson