Abstract: An integrated circuit is disclosed having through silicon vias spaced apart one from another and conductors, each coupled to one or more of the through silicon vias, the conductors in aggregate in use forming a segmented conductive plane maintained at a same potential and forming an electromagnetic shield.

Abstract: A switching power converter current limit reference circuit generates an output-referred input current reference (or an input-referred output current reference) which takes into account a converter's input voltage, output voltage, and efficiency, thereby enabling implementation of a DC, or average, input current regulation scheme. A reference current (Iref) is provided which represents the desired average current limit. Circuitry multiplies Iref and the complement of the converter's duty cycle D (1-D) together. When Iref represents a desired input current limit, the resulting product represents the average output current achievable when Iref=Iin for the prevailing duty cycle D. When Iref represents a desired output current limit, the resulting product represents the average input current achievable when Iref=Iout for prevailing duty cycle D.

Abstract: A method for controlling a switch based on transistors is disclosed. A switching circuit for switching a signal from an input port to an output port thereof is provided. A shunting circuit for switchably shunting the signal from the input port to ground is also provided. A control signal is generated for biasing a control port of the shunting circuit and an approximately complementary control signal is generated for biasing of the switching circuit to either shunt a signal received at the input port or to switch the signal to the output port. A further bias signal for biasing a port within the switching circuit along the signal path between the input port and the output.

Abstract: A switching power converter current limit reference circuit generates an output-referred input current reference (or an input-referred output current reference) which takes into account a converter's input voltage, output voltage, and efficiency, thereby enabling implementation of a DC, or average, input current regulation scheme. A reference current (Iref) is provided which represents the desired average current limit. Circuitry multiplies Iref and the complement of the converter's duty cycle D (1-D) together. When Iref represents a desired input current limit, the resulting product represents the average output current achievable when Iref=Iin for the prevailing duty cycle D. When Iref represents a desired output current limit, the resulting product represents the average input current achievable when Iref=Iout for prevailing duty cycle D.

Abstract: A method for controlling a switch based on transistors is disclosed. A switching circuit for switching a signal from an input port to an output port thereof is provided. A shunting circuit for switchably shunting the signal from the input port to ground is also provided. A control signal is generated for biasing a control port of the shunting circuit and an approximately complimentary control signal is generated for biasing of the switching circuit to either shunt a signal received at the input port or to switch the signal to the output port. A further bias signal for biasing a port within the switching circuit along the signal path between the input port and the output port is also provided.

Abstract: An integrated circuit is disclosed having through silicon vias spaced apart one from another and conductors, each coupled to one or more of the through silicon vias, the conductors in aggregate in use forming a segmented conductive plane maintained at a same potential and forming an electromagnetic shield.

Abstract: A power system comprising a front end regulator coupled to an input supply voltage (Vin) and providing a regulated input supply voltage (Vbp). The front end regulator compares the input supply voltage (Vin) and the regulated input supply voltage (Vbp) and maintains a substantially constant voltage difference between the input supply voltage (Vin) and the regulated input supply voltage (Vbp) to thereby reduce ripple of the input supply voltage (Vin). A DC-DC switching mode power converter is operatively coupled to the front end regulator and receives the regulated input supply voltage (Vbp). The DC-DC switching mode power converter thereby provides a regulated output voltage (Vout).

Abstract: Prior art architectures of power amplifiers employ a substantial die area, and utilize multiple integrated circuit technologies with a net higher manufacturing cost and large associated packaging area. A new scheme is presented wherein several sense and control signals are used to provide fine and gross control over the key figures of merit associated with integrated semiconductor power amplifiers. How and where these sense and control signals are used is crucial to achieving the most manufacturable and most economic integrated amplifier. In accordance with a first embodiment of the invention, a Dual Feedback-Low power regulation circuit for a three-stage power amplifier integrated circuit is provided. In accordance with a second embodiment of the invention, a current source feedback circuit having low RF output signal power regulation for a three-stage power amplifier integrated circuit is provided.

Abstract: Prior art architectures of power amplifiers employ a substantial die area, and utilize multiple integrated circuit technologies with a net higher manufacturing cost and large associated packaging area. A new scheme is presented wherein several sense and control signals are used to provide fine and gross control over the key figures of merit associated with integrated semiconductor power amplifiers. How and where these sense and control signals are used is crucial to achieving the most manufacturable and most economic integrated amplifier. In accordance with a first embodiment of the invention, a Dual Feedback-Low power regulation circuit for a three-stage power amplifier integrated circuit is provided. In accordance with a second embodiment of the invention, a current source feedback circuit having low RF output signal power regulation for a three-stage power amplifier integrated circuit is provided.

Abstract: Prior art architectures of power amplifiers employ a substantial die area, and utilize multiple integrated circuit technologies with a net higher manufacturing cost and large associated packaging area. A new scheme is presented wherein several sense and control signals are used to provide fine and gross control over the key figures of merit associated with integrated semiconductor power amplifiers. How and where these sense and control signals are used is crucial to achieving the most manufacturable and most economic integrated amplifier. In accordance with a first embodiment of the invention, a Dual Feedback-Low power regulation circuit for a three-stage power amplifier integrated circuit is provided. In accordance with a second embodiment of the invention, a current source feedback circuit having low RF output signal power regulation for a three-stage power amplifier integrated circuit is provided.

Abstract: Prior art architectures of power amplifiers employ a substantial die area, and utilize multiple integrated circuit technologies with a net higher manufacturing cost and large associated packaging area. A new scheme is presented wherein several sense and control signals are used to provide fine and gross control over the key figures of merit associated with integrated semiconductor power amplifiers. How and where these sense and control signals are used is crucial to achieving the most manufacturable and most economic integrated amplifier. In accordance with a first embodiment of the invention, a Dual Feedback-Low power regulation circuit for a three-stage power amplifier integrated circuit is provided. In accordance with a second embodiment of the invention, a current source feedback circuit having low RF output signal power regulation for a three-stage power amplifier integrated circuit is provided.

Abstract: Prior art architectures of power amplifiers employ a substantial die area, and utilize multiple integrated circuit technologies with a net higher manufacturing cost and large associated packaging area. A new scheme is presented wherein several sense and control signals are used to provide fine and gross control over the key figures of merit associated with integrated semiconductor power amplifiers. How and where these sense and control signals are used is crucial to achieving the most manufacturable and most economic integrated amplifier. In accordance with a first embodiment of the invention, a Dual Feedback-Low power regulation circuit for a three-stage power amplifier integrated circuit is provided. In accordance with a second embodiment of the invention, a current source feedback circuit having low RF output signal power regulation for a three-stage power amplifier integrated circuit is provided.

Abstract: Prior art architectures of power amplifiers employ a substantial die area, and utilize multiple integrated circuit technologies with a net higher manufacturing cost and large associated packaging area. A new scheme is presented wherein several sense and control signals are used to provide fine and gross control over the key figures of merit associated with integrated semiconductor power amplifiers. How and where these sense and control signals are used is crucial to achieving the most manufacturable and most economic integrated amplifier. In accordance with a first embodiment of the invention, a Dual Feedback-Low power regulation circuit for a three-stage power amplifier integrated circuit is provided. In accordance with a second embodiment of the invention, a current source feedback circuit having low RF output signal power regulation for a three-stage power amplifier integrated circuit is provided.

Abstract: An amplifier having a two different single crystal semiconductor substrates. A first one of the substrates has formed thereon at least one input signal amplifying device, such device comprising a bipolar transistor. A second one of the substrates is a material different from the material of the first substrate. A current mirror is included. The current mirror includes a plurality of electrically interconnected active devices, one portion of the devices being bipolar devices formed on the first substrate and another portion of the active devices comprising an insulated gate field effect transistor formed on the second substrate. The first single crystal substrate is III-V material and the second single crystal substrate is silicon. The bipolar devices are HBTs. The insulated gate field effect transistor is a MOS device. This configuration minimizes the effect of temperature, voltage and process variations on critical transistor operating currents.