Patents by Inventor Michael Meyer-Pundsack
Michael Meyer-Pundsack has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9251553Abstract: A pipelined video pre-processor includes a plurality of configurable image-processing modules. The modules may be configured using direct processor control, DMA access, or both. A block-control list, accessible via DMA, facilitates configuration of the modules in a manner similar to direct processor control. Parameters in the modules may be updated on a frame-by-frame basis.Type: GrantFiled: October 14, 2012Date of Patent: February 2, 2016Assignee: Analog Devices, Inc.Inventors: Satishchandra G. Rao, Boris Lerner, Robert Bushey, Michael Meyer-Pundsack, Benno Kusstatscher, Sreejith Kazhayil, Gokul Muthusamy, Gopal Karanam, Praveen Sanjeev
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Publication number: 20150147005Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.Type: ApplicationFiled: February 2, 2015Publication date: May 28, 2015Applicant: ANALOG DEVICES GLOBALInventors: Boris Lerner, Michael Meyer-Pundsack, Gopal Gudhdur Karanam, Pradip Thaker
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Patent number: 8947446Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.Type: GrantFiled: May 13, 2013Date of Patent: February 3, 2015Assignee: Analog Devices TechnologyInventors: Boris Lerner, Michael Meyer-Pundsack, Gopal Gudhur Karanam, Pradip Thacker
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Patent number: 8766992Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.Type: GrantFiled: May 13, 2013Date of Patent: July 1, 2014Assignee: Analog Devices, Inc.Inventors: Boris Lerner, Michael Meyer-Pundsack, Gopal Gudhur Karanam, Pradip Thaker
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Publication number: 20130342551Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.Type: ApplicationFiled: May 13, 2013Publication date: December 26, 2013Applicant: ANALOG DEVICES TECHNOLOGYInventors: Boris Lerner, Michael Meyer-Pundsack, Gopal Gudhur Karanam, Pradip Thaker
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Publication number: 20130249923Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.Type: ApplicationFiled: May 13, 2013Publication date: September 26, 2013Applicant: ANALOG DEVICES TECHNOLOGYInventors: Michael Meyer-Pundsack, Boris Lerner, Gopal Gudhur Karanam, Pradip Thacker
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Patent number: 8441492Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.Type: GrantFiled: January 20, 2012Date of Patent: May 14, 2013Assignee: Analog Devices Inc.Inventors: Michael Meyer-Pundsack, Boris Lerner, Gopal Gudhur Karanam, Pradip Thaker
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Publication number: 20120176389Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.Type: ApplicationFiled: January 20, 2012Publication date: July 12, 2012Applicant: Analog Devices, Inc.Inventors: Boris Lerner, Pradip Thaker, Gopal Gudhur Karanam, Michael Meyer-Pundsack
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Patent number: 8130229Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.Type: GrantFiled: November 17, 2009Date of Patent: March 6, 2012Assignee: Analog Devices, Inc.Inventors: Boris Lerner, Pradip Thaker, Gopal Gudhur Karanam, Michael Meyer-Pundsack
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Publication number: 20110115804Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.Type: ApplicationFiled: November 17, 2009Publication date: May 19, 2011Inventors: Boris Lerner, Pradip Thaker, Gopal Gudhur Karanam, Michael Meyer-Pundsack