Patents by Inventor Michael Mi. Tsao

Michael Mi. Tsao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9229877
    Abstract: A method for configuring a large hybrid memory subsystem having a large cache size in a computing system where one or more performance metrics of the computing system are expressed as an explicit function of configuration parameters of the memory subsystem and workload parameters of the memory subsystem. The computing system hosts applications that utilize the memory subsystem, and the performance metrics cover the use of the memory subsystem by the applications. A performance goal containing values for the performance metric is identified for the computing system. These values for the performance metrics are used in the explicit function of performance metrics, configuration parameters and workload parameters to calculate values for the configuration parameters that achieve the identified performance goal. The calculated values of the configuration parameters are implemented in the memory subsystem.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: January 5, 2016
    Inventors: John Alan Bivens, Parijat Dube, Michael Mi Tsao, Li Zhang
  • Patent number: 8954683
    Abstract: A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. When two translation table entries reference identical fragments in a memory block, one of the translation table entries is changed to refer to the same memory block referenced in the other translation table entry, which frees up a memory block. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries. When a translation table has a private delta, its delta bit is set.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: February 10, 2015
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Bulent Abali, James A. Marcella, Michael Mi Tsao, Steven M. Wheeler
  • Publication number: 20130318305
    Abstract: A method for configuring a large hybrid memory subsystem having a large cache size in a computing system where one or more performance metrics of the computing system are expressed as an explicit function of configuration parameters of the memory subsystem and workload parameters of the memory subsystem. The computing system hosts applications that utilize the memory subsystem, and the performance metrics cover the use of the memory subsystem by the applications. A performance goal containing values for the performance metric is identified for the computing system. These values for the performance metrics are used in the explicit function of performance metrics, configuration parameters and workload parameters to calculate values for the configuration parameters that achieve the identified performance goal. The calculated values of the configuration parameters are implemented in the memory subsystem.
    Type: Application
    Filed: July 30, 2013
    Publication date: November 28, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Alan Bivens, Parijat Dube, Michael Mi Tsao, Li Zhang
  • Patent number: 8527704
    Abstract: A method for configuring a large hybrid memory subsystem having a large cache size in a computing system where one or more performance metrics of the computing system are expressed as an explicit function of configuration parameters of the memory subsystem and workload parameters of the memory subsystem. The computing system hosts applications that utilize the memory subsystem, and the performance metrics cover the use of the memory subsystem by the applications. A performance goal containing values for the performance metric is identified for the computing system. These values for the performance metrics are used in the explicit function of performance metrics, configuration parameters and workload parameters to calculate values for the configuration parameters that achieve the identified performance goal. The calculated values of the configuration parameters are implemented in the memory subsystem.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: September 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: John Alan Bivens, Parijat Dube, Michael Mi Tsao, Li Zhang
  • Publication number: 20120124318
    Abstract: A method for configuring a large hybrid memory subsystem having a large cache size in a computing system where one or more performance metrics of the computing system are expressed as an explicit function of configuration parameters of the memory subsystem and workload parameters of the memory subsystem. The computing system hosts applications that utilize the memory subsystem, and the performance metrics cover the use of the memory subsystem by the applications. A performance goal containing values for the performance metric is identified for the computing system. These values for the performance metrics are used in the explicit function of performance metrics, configuration parameters and workload parameters to calculate values for the configuration parameters that achieve the identified performance goal. The calculated values of the configuration parameters are implemented in the memory subsystem.
    Type: Application
    Filed: November 11, 2010
    Publication date: May 17, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Alan Bivens, Parijat Dube, Michael Mi Tsao, Li Zhang
  • Patent number: 5680597
    Abstract: A single instruction multiple data stream ("SIMD") processor includes multiple processing elements ("PEs"). Each PE includes a memory, a first multiplexer, an instruction register, a local instruction buffer for storing an instruction and a unit for modifying the instruction, in its entirety, to create a modified instruction. The modified instruction is stored in the local instruction buffer until it is executed. This structure modifies the instruction broadcast from the central controller of an SIMD computer in its entirety and creates modified instructions which can be unique to each PE.
    Type: Grant
    Filed: January 26, 1995
    Date of Patent: October 21, 1997
    Assignee: International Business Machines Corporation
    Inventors: Manoj Kumar, Michael Mi. Tsao