Patents by Inventor Michael Moriaud

Michael Moriaud has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Writing data and resilience bits to register memory
    Patent number: 12724708
    Abstract: In an electronic system, data is written to a write address in register memory. Chunks of the data are decomposed into a plurality of data sub-granules. Bits of the write address are distributed to the data sub-granules. An address sub-granule is created for any bits of the write address that were not distributed to the data sub-granules. A resilience algorithm is used to compute resilience bits for each of the sub-granules. The chunks and the resilience bits are written to the register memory.
    Type: Grant
    Filed: March 30, 2025
    Date of Patent: September 1, 2026
    Assignee: ARTERIS, INC.
    Inventors: Xavier Van Ruymbeke, Michael Moriaud, Frederic Greus, Sylvain Meliciani