Abstract: According to one embodiment a central processing unit (CPU) is disclosed. The CPU includes a translation lookaside buffer (TLB). The TLB predicts a set index value prior to the generation of an effective address.

Abstract: A two-stage arbiter system comprises a first-stage arbiter to grant a request to one of a plurality of requesters in accordance with a first arbitration scheme and a second-stage arbiter to grant one of the remaining requests in accordance with a second arbitration scheme. The first arbitration scheme may be a fast arbitration scheme such as a fixed-priority scheme, and the second arbitration scheme may be a rotating priority-based arbitration scheme or a least-recently-granted arbitration scheme. The first-stage arbiter may operate in a first pipelined stage, and the second-stage arbiter may operate in a second pipelined stage. Two-stage arbitration may help improve access of lower-priority requestors in a pipelined system. In one embodiment, a rotating-priority arbitrator includes a pseudo-random number generator to generate an amount for rotating priorities prior to arbitration. The rotating-priority arbiter may use either a counter or linear-feedback shift register to rotate priorities of requests.

Abstract: A processor includes a multi-level cache hierarchy where locality information property such as a Low Locality of Reference (LLR) property is associated with a cache line. The LLR cache line retains the locality information and may move back and forth within the cache hierarchy until evicted from the outer-most level of the cache hierarchy.

Abstract: A cache controller prevents the use of data in a write-back cache memory from being propagated until the data is backed-up in a main memory. Control bits inhibit portions of the cache memory from being accessed.

Abstract: A cover system (10) for an open-topped container, such as a transfer trailer (T), includes a cover (11) carried by a support frame (13) pivotably mounted to the container. The support frame includes a triangular construct (20) at the opposite ends of the container to improve the rigidity of the cover system. A continuous drive shaft (28) extends along the length of the container and is connected to the support frame. A drive assembly (15) rotates the continuous drive shaft to pivot the cover between retracted and deployed positions. The drive assembly is reversible to accommodate covers mounted on either side of the container.

Abstract: An integrated circuit includes power gating circuits for coupling an associated circuit block with a power supply voltage. The power gating circuits also generate power consumption measurements for the associated circuit blocks. A power manager for the integrated circuit may manage the overall power consumption of the integrated circuit and may individually turn on and off the circuit blocks using the power gating circuits.

Abstract: A hybrid branch predictor capable of performing static and dynamic branch prediction operates in a single pipeline stage.

Abstract: Briefly, in accordance with an embodiment of the invention, a system and method to order memory operations is provided. The method may include using at least one signal to indicate that a particular kind of memory operation is not globally observable but is observable by at least one processor of the system. The system may include a processor to use at least one signal for memory consistency, wherein the at least one signal indicates that a particular kind of memory operation is not globally observable in the system but is observable by at least one processor of the system. Other embodiments are described and claimed.

Abstract: Briefly, in accordance with an embodiment of the invention, a method and apparatus to write back data is provided. The method may include setting a status corresponding to a block of data in response to a change in address mapping to indicate that the block of data is pending write back. The apparatus may include a storage area to store a status associated with a block of data to indicate that the block of data is pending write back and is not accessible with the current address mapping. Other embodiments are described and claimed.

Abstract: A semi-trace cache combines elements and features of an instruction cache and a trace cache. An ICache portion of the semi-trace cache is filled with instructions fetched from the next level of the memory hierarchy while a TCache portion is filled with traces gleaned either from the actual stream of retired instructions or predicted before execution.

Abstract: A processing engine fetches one or more lines of software instructions into an instruction cache. Based on the contents of the cache, potentially needed functional units are identified as functional units that are operable to execute at least one software instruction stored within the instruction cache. Unneeded functional units are identified as functional units that are not operable to execute a software instruction stored within the instruction cache. A power increase is initiated for selected ones of the potentially needed functional units that are determined to be in a low power state. A power decrease is initiated for selected ones of the unneeded functional units that are determined to be in an operable power state.

Abstract: A cover system for an open-topped container, such as a transfer trailer, includes a cover carried by a support frame pivotably mounted to the container. The support frame includes a triangular construct at the opposite ends of the container to improve the rigidity of the cover system. A continuous drive shaft extends along the length of the container and is connected to the support frame. A drive assembly rotates the continuous drive shaft to pivot the cover between retracted and deployed positions. The drive assembly is reversible to accommodate covers mounted on either side of the container.

Abstract: According to one embodiment a central processing unit (CPU) is disclosed. The CPU includes a translation lookaside buffer (TLB). The TLB predicts a set index value prior to the generation of an effective address.

Abstract: Briefly, in accordance with an embodiment of the invention, an apparatus and method to enable execution of a thread in a multi-threaded computer system is provided. The method may include enabling execution of a non-executing thread based at least on whether a hardware resource is or will be available to an instruction of the non-executing thread. The apparatus may include a thread dispatch circuit to enable execution of a pending thread based at least on whether a hardware resource is or will be available to an instruction of the non-executing thread.

Abstract: In one embodiment, the present invention includes a method to determine whether execution of an instruction of a first thread may require a long latency and switch to a second thread if the instruction may require the long latency. In certain embodiments, at least one additional instruction may be executed in the first thread while preparing to switch threads.

Abstract: The present invention provides inexpensive polyolefin films with a built in adhesive for covering stationary products wherein the polyolefin films can be welded through the adhesive using radio frequency resulting in a stationery product that provides improved hinge durability, low temperature crack resistance and the elimination of image transfer. Also provided are methods of manufacture of the films and a method for the welding of the films around a rigid support material such as chipboard using a radio frequency signal.

Abstract: A laser emitting visual display for a music system including a housing with a hollow interior and transparent window. A plurality of lasers are coupled within the housing and disposed to emit high intensity light beams generally towards the transparent window when actuated. Also included is a control mechanism situated within the housing and coupled to a current source, an output of a music system, and each of the lasers. The mechanism is adapted to actuate different lasers depending on the frequency and volume of a signal received via the output of the music system thereby effecting a coincident visual and audio spectacle.