Patents by Inventor Michael Mostovoy

Michael Mostovoy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200126936
    Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Hem Takiar, Michael Mostovoy, Emilio Yero, Gokul Kumar, Yan Li
  • Publication number: 20200006268
    Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Hem Takiar, Michael Mostovoy, Emilio Yero, Gokul Kumar, Yan Li
  • Patent number: 10522489
    Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: December 31, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Hem Takiar, Michael Mostovoy, Emilio Yero, Gokul Kumar, Yan Li
  • Publication number: 20190341375
    Abstract: A semiconductor device is disclosed including one or more integrated memory modules. Each integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the first die may be flip-chip bonded to the second die.
    Type: Application
    Filed: June 28, 2018
    Publication date: November 7, 2019
    Applicant: Western Digital Technologies, Inc.
    Inventors: Toshiki Hirano, Gokul Kumar, Akio Nishida, Yan Li, Michael Mostovoy
  • Patent number: 10381327
    Abstract: A non-volatile storage system includes a plurality of memory dies and an interface circuit. Each memory die includes a wide I/O interface electrically coupled to another wide I/O interface of another memory die of the plurality of memory dies. The interface circuit is physically separate from the memory dies. The interface circuit includes a first interface and a second interface. The first interface comprises a wide I/O interface electrically coupled to a wide I/O interface of at least one of the memory dies of the plurality of memory dies. The second interface is a narrow I/O interface configured to communicate with an external circuit.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: August 13, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Venkatesh P. Ramachandra, Michael Mostovoy, Hem Takiar, Gokul Kumar, Vinayak Ghatawade
  • Patent number: 10249592
    Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.
    Type: Grant
    Filed: February 18, 2018
    Date of Patent: April 2, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Michael Mostovoy, Gokul Kumar, Ning Ye, Hem Takiar, Venkatesh P. Ramachandra, Vinayak Ghatawade, Chih-Chin Liao
  • Publication number: 20180174996
    Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.
    Type: Application
    Filed: February 18, 2018
    Publication date: June 21, 2018
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Michael Mostovoy, Gokul Kumar, Ning Ye, Hem Takiar, Venkatesh P. Ramachandra, Vinayak Ghatawade, Chih-Chin Liao
  • Publication number: 20180102344
    Abstract: A non-volatile storage system includes a plurality of memory dies and an interface circuit. Each memory die includes a wide I/O interface electrically coupled to another wide I/O interface of another memory die of the plurality of memory dies. The interface circuit is physically separate from the memory dies. The interface circuit includes a first interface and a second interface. The first interface comprises a wide I/O interface electrically coupled to a wide I/O interface of at least one of the memory dies of the plurality of memory dies. The second interface is a narrow I/O interface configured to communicate with an external circuit.
    Type: Application
    Filed: October 6, 2016
    Publication date: April 12, 2018
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Venkatesh P. Ramachandra, Michael Mostovoy, Hem Takiar, Gokul Kumar, Vinayak Ghatawade
  • Patent number: 9899347
    Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: February 20, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Michael Mostovoy, Gokul Kumar, Ning Ye, Hem Takiar, Venkatesh P. Ramachandra, Vinayak Ghatawade, Chih-Chin Liao
  • Publication number: 20120137152
    Abstract: A controller (e.g., a memory controller) includes initial error analysis logic (e.g., a section of a Reed Solomon or BCH codeword decoder) that determines an error count for a data element. The data element may be data stored in the memory of a memory device (e.g., a flash memory device) that incorporates the controller. Comparison logic in the controller determines when the error count exceeds a power control threshold. When the error count exceeds the power control threshold, control logic in the controller reduces the operational speed of subsequent error analysis logic (e.g., a different section of the Reed Solomon or BCH codeword decoder) for the data element. For example, the subsequent error analysis logic may be error locator logic, such as Chien search logic, that determines where the errors exist in the data element.
    Type: Application
    Filed: December 7, 2011
    Publication date: May 31, 2012
    Inventors: Itai Dror, Alexander Berger, Michael Mostovoy, Yoav Weinberg
  • Patent number: 7904719
    Abstract: An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field, in such a way as to simplify the flow of operands, by performing a multiple anticipatory function to enhance the previous modular multiplication procedures.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: March 8, 2011
    Assignee: SanDisk IL Ltd.
    Inventors: Itai Dror, Carmi David Gressel, Michael Mostovoy, Alexay Molchanov
  • Publication number: 20060269054
    Abstract: An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field, in such a way as to simplify the flow of operands, by performing a multiple anticipatory function to enhance the previous modular multiplication procedures.
    Type: Application
    Filed: August 1, 2006
    Publication date: November 30, 2006
    Inventors: Itai Dror, Carmi Gressel, Michael Mostovoy, Alexay Molchanov
  • Patent number: 7111166
    Abstract: An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field, in such a way as to simplify the flow of operands, by performing a multiple anticipatory function to enhance the previous modular multiplication procedures.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: September 19, 2006
    Assignee: Fortress U&T Div. M-Systems Flash Disk Pioneers Ltd.
    Inventors: Itai Dror, Carmi David Gressel, Michael Mostovoy, Alexey Molchanov
  • Patent number: 6748410
    Abstract: This invention discloses apparatus and methods for accelerating processing, loading and unloading of data, from and to a plurality of memory addresses in a CPU having an accumulator, and to a memory-mapped coprocessing device for continuous integer computations.
    Type: Grant
    Filed: January 10, 2000
    Date of Patent: June 8, 2004
    Assignee: M-Systems Flash Disk Pioneers, Ltd.
    Inventors: Carmi David Gressel, Isaac Hadad, Itai Dror, Alexey Molchanov, Michael Mostovoy
  • Publication number: 20020039418
    Abstract: An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field, in such a way as to simplify the flow of operands, by performing a multiple anticipatory function to enhance the previous modular multiplication procedures.
    Type: Application
    Filed: May 14, 2001
    Publication date: April 4, 2002
    Applicant: FORTRESS U&T Div. M-SYSTEMS FLASH DISK PIONEERS LTD.
    Inventors: Itai Dror, Carmi David Gressel, Michael Mostovoy, Alexey Molchanov