Patents by Inventor Michael Mostovoy
Michael Mostovoy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230288949Abstract: Various embodiments of the present disclosure relate to apparatuses and methods for regulators providing shared current from multiple input supplies. A regulator can include a first portion configured to receive a first supply voltage and to output a first current drawn from the first supply voltage by a load, and a second portion configured to receive a second supply voltage. The regulator can include a current control circuit configured to, responsive to a load current corresponding the load meeting a particular criteria, initiate current sharing such that the load current is subsequently shared between the first supply voltage and the second supply voltage.Type: ApplicationFiled: July 28, 2022Publication date: September 14, 2023Inventors: Ekram H. Bhuiyan, Jayaprakash Naradasi, Srinivasa Rao Sabbineni, Michael Mostovoy
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Patent number: 10930607Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.Type: GrantFiled: December 20, 2019Date of Patent: February 23, 2021Assignee: Western Digital Technologies, Inc.Inventors: Hem Takiar, Michael Mostovoy, Emilio Yero, Gokul Kumar, Yan Li
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Patent number: 10923462Abstract: A semiconductor device is disclosed including one or more integrated memory modules. Each integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the first die may be flip-chip bonded to the second die.Type: GrantFiled: June 28, 2018Date of Patent: February 16, 2021Assignee: Western Digital Technologies, Inc.Inventors: Toshiki Hirano, Gokul Kumar, Akio Nishida, Yan Li, Michael Mostovoy
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Publication number: 20200126936Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.Type: ApplicationFiled: December 20, 2019Publication date: April 23, 2020Applicant: Western Digital Technologies, Inc.Inventors: Hem Takiar, Michael Mostovoy, Emilio Yero, Gokul Kumar, Yan Li
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Publication number: 20200006268Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Applicant: Western Digital Technologies, Inc.Inventors: Hem Takiar, Michael Mostovoy, Emilio Yero, Gokul Kumar, Yan Li
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Patent number: 10522489Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.Type: GrantFiled: June 28, 2018Date of Patent: December 31, 2019Assignee: Western Digital Technologies, Inc.Inventors: Hem Takiar, Michael Mostovoy, Emilio Yero, Gokul Kumar, Yan Li
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Publication number: 20190341375Abstract: A semiconductor device is disclosed including one or more integrated memory modules. Each integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the first die may be flip-chip bonded to the second die.Type: ApplicationFiled: June 28, 2018Publication date: November 7, 2019Applicant: Western Digital Technologies, Inc.Inventors: Toshiki Hirano, Gokul Kumar, Akio Nishida, Yan Li, Michael Mostovoy
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Patent number: 10381327Abstract: A non-volatile storage system includes a plurality of memory dies and an interface circuit. Each memory die includes a wide I/O interface electrically coupled to another wide I/O interface of another memory die of the plurality of memory dies. The interface circuit is physically separate from the memory dies. The interface circuit includes a first interface and a second interface. The first interface comprises a wide I/O interface electrically coupled to a wide I/O interface of at least one of the memory dies of the plurality of memory dies. The second interface is a narrow I/O interface configured to communicate with an external circuit.Type: GrantFiled: October 6, 2016Date of Patent: August 13, 2019Assignee: SanDisk Technologies LLCInventors: Venkatesh P. Ramachandra, Michael Mostovoy, Hem Takiar, Gokul Kumar, Vinayak Ghatawade
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Patent number: 10249592Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.Type: GrantFiled: February 18, 2018Date of Patent: April 2, 2019Assignee: SanDisk Technologies LLCInventors: Michael Mostovoy, Gokul Kumar, Ning Ye, Hem Takiar, Venkatesh P. Ramachandra, Vinayak Ghatawade, Chih-Chin Liao
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Publication number: 20180174996Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.Type: ApplicationFiled: February 18, 2018Publication date: June 21, 2018Applicant: SANDISK TECHNOLOGIES LLCInventors: Michael Mostovoy, Gokul Kumar, Ning Ye, Hem Takiar, Venkatesh P. Ramachandra, Vinayak Ghatawade, Chih-Chin Liao
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Publication number: 20180102344Abstract: A non-volatile storage system includes a plurality of memory dies and an interface circuit. Each memory die includes a wide I/O interface electrically coupled to another wide I/O interface of another memory die of the plurality of memory dies. The interface circuit is physically separate from the memory dies. The interface circuit includes a first interface and a second interface. The first interface comprises a wide I/O interface electrically coupled to a wide I/O interface of at least one of the memory dies of the plurality of memory dies. The second interface is a narrow I/O interface configured to communicate with an external circuit.Type: ApplicationFiled: October 6, 2016Publication date: April 12, 2018Applicant: SANDISK TECHNOLOGIES LLCInventors: Venkatesh P. Ramachandra, Michael Mostovoy, Hem Takiar, Gokul Kumar, Vinayak Ghatawade
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Patent number: 9899347Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.Type: GrantFiled: March 9, 2017Date of Patent: February 20, 2018Assignee: SanDisk Technologies LLCInventors: Michael Mostovoy, Gokul Kumar, Ning Ye, Hem Takiar, Venkatesh P. Ramachandra, Vinayak Ghatawade, Chih-Chin Liao
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Publication number: 20120137152Abstract: A controller (e.g., a memory controller) includes initial error analysis logic (e.g., a section of a Reed Solomon or BCH codeword decoder) that determines an error count for a data element. The data element may be data stored in the memory of a memory device (e.g., a flash memory device) that incorporates the controller. Comparison logic in the controller determines when the error count exceeds a power control threshold. When the error count exceeds the power control threshold, control logic in the controller reduces the operational speed of subsequent error analysis logic (e.g., a different section of the Reed Solomon or BCH codeword decoder) for the data element. For example, the subsequent error analysis logic may be error locator logic, such as Chien search logic, that determines where the errors exist in the data element.Type: ApplicationFiled: December 7, 2011Publication date: May 31, 2012Inventors: Itai Dror, Alexander Berger, Michael Mostovoy, Yoav Weinberg
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Patent number: 7904719Abstract: An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field, in such a way as to simplify the flow of operands, by performing a multiple anticipatory function to enhance the previous modular multiplication procedures.Type: GrantFiled: July 31, 2006Date of Patent: March 8, 2011Assignee: SanDisk IL Ltd.Inventors: Itai Dror, Carmi David Gressel, Michael Mostovoy, Alexay Molchanov
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Publication number: 20060269054Abstract: An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field, in such a way as to simplify the flow of operands, by performing a multiple anticipatory function to enhance the previous modular multiplication procedures.Type: ApplicationFiled: August 1, 2006Publication date: November 30, 2006Inventors: Itai Dror, Carmi Gressel, Michael Mostovoy, Alexay Molchanov
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Patent number: 7111166Abstract: An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field, in such a way as to simplify the flow of operands, by performing a multiple anticipatory function to enhance the previous modular multiplication procedures.Type: GrantFiled: May 14, 2001Date of Patent: September 19, 2006Assignee: Fortress U&T Div. M-Systems Flash Disk Pioneers Ltd.Inventors: Itai Dror, Carmi David Gressel, Michael Mostovoy, Alexey Molchanov
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Patent number: 6748410Abstract: This invention discloses apparatus and methods for accelerating processing, loading and unloading of data, from and to a plurality of memory addresses in a CPU having an accumulator, and to a memory-mapped coprocessing device for continuous integer computations.Type: GrantFiled: January 10, 2000Date of Patent: June 8, 2004Assignee: M-Systems Flash Disk Pioneers, Ltd.Inventors: Carmi David Gressel, Isaac Hadad, Itai Dror, Alexey Molchanov, Michael Mostovoy
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Publication number: 20020039418Abstract: An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field, in such a way as to simplify the flow of operands, by performing a multiple anticipatory function to enhance the previous modular multiplication procedures.Type: ApplicationFiled: May 14, 2001Publication date: April 4, 2002Applicant: FORTRESS U&T Div. M-SYSTEMS FLASH DISK PIONEERS LTD.Inventors: Itai Dror, Carmi David Gressel, Michael Mostovoy, Alexey Molchanov