Abstract: Described herein, in one embodiment, is a graphics processor comprising a plurality of dies integrated in a package, at least one die of the plurality of dies functionally heterogeneous relative to at least one other die of the plurality of dies and manufactured with a different process technology than the at least one other die.

Abstract: Described herein, in one embodiment, are techniques to facilitate the partial powerdown of sub-components of an execution unit or other graphics processing resource based on the workload to be executed. In another embodiment, granular dynamic voltage and frequency scaling is enabled in which the voltage and frequency of groups of processing resources within a graphics processor can be separately scaled.

Abstract: The systems and methods described herein provide the ability to detect a clocking element fault within an IC device and switch to an alternate clock. In response to detection of a fault in a phase-lock-loop (PLL) clocking element, the device may switch to an alternate clock so that error reporting logic can make forward progress on generating error message. The error message may be generated within an Intellectual Property (IP) cores (e.g., IP blocks), and may send the error message from the IP core to a system-on-a-chip (SOC), such as through an SOC Functional Safety (FuSA) error reporting infrastructure. In various examples, the clocking error may also be output to a hardware SOC pin, such as to provide a redundant path for error indication.

Abstract: Various systems and methods for managing graphics subsystems are described herein. A system for managing graphics subsystems of a compute device includes a display controller operable to: receive an indication that a first display of the compute device has been activated; enable a power management feature in a display controller, the power management feature to reduce power consumption of the display controller and associated components, and the power management feature to reduce graphics memory bandwidth usage; receive an indication that a second display has been activated with the first display; and maintain the power management feature for at least the first display.

Abstract: Blanking on a display device (for example, a display monitor or a display panel) in a computer system is avoided by performing a configuration change during the vertical blanking period of a subsequent frame. Upon detecting a change in configuration of one or more display devices in the computer system, a display engine clock phase-locked loop is turned off, reprogrammed to a new frequency and relocked during the vertical blanking period of the subsequent frame.

Abstract: In embodiments, an apparatus may comprise random access memory (RAM); an error detecting and/or correcting code (EDCC) encoder to generate and add an error detecting and/or correcting code to a datum being written into the memory for storage; and an EDCC decoder to use the error detecting and/or correcting code added to the datum to correct one or more bits of error in the datum when the datum with the added error detecting and/or correcting code is read back from the RAM. Further, the apparatus may include an error detection and/or correction checker to inject one or more bits of error into the datum when the datum with the added error and/or correcting code is read back from the RAM, and check whether the EDCC decoder is able to correct the one or more bits of error injected into the datum.

Abstract: Various systems and methods for error handling are described herein. A system for error reporting and handling includes a common error handler that handles errors for a plurality of hardware devices, where the common error handler is operable with other parallel error reporting and handling mechanisms. The common error handler may be used to receive an error message from a hardware device, the error message related to an error; identify a source of the error message; identify a class of the error; identify an error definition of the error; determine whether the error requires a diagnostics operation as part of the error handling; initiate the diagnostics operation when the error requires the diagnostics operation; and clear the error at the hardware device.

Abstract: Technologies for end-to-end display integrity verification include a computing device with a display controller coupled to a display by a physical link. The computing device generates pixel data in a data buffer in memory, and the display controller outputs a pixel signal on the physical link based on the pixel data using a physical interface. The display receives the pixel signal and displays a corresponding image. A splicer is connected to the physical link and repeats the pixel signal to an I/O port of the computing device. The I/O port may be a USB Type-C port. The computing device compares pixel data received by the I/O port to the pixel data in the data buffer. The computing device may calculate checksums of the pixel data. If the pixel data does not match, the computing device may indicate a display integrity failure. Other embodiments are described and claimed.

Abstract: The systems and methods described herein provide the ability to detect a clocking element fault within an IC device and switch to an alternate clock. In response to detection of a fault in a phase-lock-loop (PLL) clocking element, the device may switch to an alternate clock so that error reporting logic can make forward progress on generating error message. The error message may be generated within an Intellectual Property (IP) cores (e.g., IP blocks), and may send the error message from the IP core to a system-on-a-chip (SOC), such as through an SOC Functional Safety (FuSA) error reporting infrastructure. In various examples, the clocking error may also be output to a hardware SOC pin, such as to provide a redundant path for error indication.

Abstract: Various techniques for providing a fault-tolerant graphics display engine are disclosed herein. In an example, a machine identifies a buffer under-run at a data buffer (DBUF) of a display engine. The machine adjusts a latency tolerance of the DBUF in response to identifying the buffer under-run. The machine determines that the buffer under-run at the DBUF persists after adjusting the latency tolerance. The machine determines whether a preset correction limit has been reached. If the preset correction limit has not been reached, the machine further adjusts the latency tolerance of the DBUF. If the preset correction limit has been reached, the machine removes, from a visual output associated with the display engine, one or more non-critical display assets.

Abstract: Various techniques for providing a fault-tolerant graphics display engine are disclosed herein. In an example, a machine identifies a buffer under-run at a data buffer (DBUF) of a display engine. The machine adjusts a latency tolerance of the DBUF in response to identifying the buffer under-run. The machine determines that the buffer under-run at the DBUF persists after adjusting the latency tolerance. The machine determines whether a preset correction limit has been reached. If the preset correction limit has not been reached, the machine further adjusts the latency tolerance of the DBUF. If the preset correction limit has been reached, the machine removes, from a visual output associated with the display engine, one or more non-critical display assets.

Abstract: Various systems and methods for error handling are described herein. A system for error reporting and handling includes a common error handler that handles errors for a plurality of hardware devices, where the common error handler is operable with other parallel error reporting and handling mechanisms. The common error handler may be used to receive an error message from a hardware device, the error message related to an error; identify a source of the error message; identify a class of the error; identify an error definition of the error; determine whether the error requires a diagnostics operation as part of the error handling; initiate the diagnostics operation when the error requires the diagnostics operation; and clear the error at the hardware device.

Abstract: Technologies for end-to-end display integrity verification include a computing device with a display controller coupled to a display by a physical link. The computing device generates pixel data in a data buffer in memory, and the display controller outputs a pixel signal on the physical link based on the pixel data using a physical interface. The display receives the pixel signal and displays a corresponding image. A splicer is connected to the physical link and repeats the pixel signal to an I/O port of the computing device. The I/O port may be a USB Type-C port. The computing device compares pixel data received by the I/O port to the pixel data in the data buffer. The computing device may calculate checksums of the pixel data. If the pixel data does not match, the computing device may indicate a display integrity failure. Other embodiments are described and claimed.

Abstract: In embodiments, an apparatus may comprise random access memory (RAM); an error detecting and/or correcting code (EDCC) encoder to generate and add an error detecting and/or correcting code to a datum being written into the memory for storage; and an EDCC decoder to use the error detecting and/or correcting code added to the datum to correct one or more bits of error in the datum when the datum with the added error detecting and/or correcting code is read back from the RAM. Further, the apparatus may include an error detection and/or correction checker to inject one or more bits of error into the datum when the datum with the added error and/or correcting code is read back from the RAM, and check whether the EDCC decoder is able to correct the one or more bits of error injected into the datum.

Abstract: Various systems and methods for managing graphics subsystems are described herein. A system for managing graphics subsystems of a compute device includes a display controller operable to: receive an indication that a first display of the compute device has been activated; enable a power management feature in a display controller, the power management feature to reduce power consumption of the display controller and associated components, and the power management feature to reduce graphics memory bandwidth usage; receive an indication that a second display has been activated with the first display; and maintain the power management feature for at least the first display.

Abstract: In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.

Abstract: In an embodiment, the present invention includes a processor having a first domain with at least one core to execute instructions, a second domain coupled to the first domain and having at least one non-core circuit, and a power control unit (PCU) coupled to the first and second domains. The PCU may include a power sharing logic to receive encoded power consumption information from the second domain and to calculate an available power budget for the first domain based at least in part on the encoded power consumption information. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed.