Abstract: A microprocessor includes a macro-op (MOP) cache (MOC) comprising a set-associative MOC tag RAM (MTR) and a MOC data RAM (MDR) managed as a pool of MDR entries. A MOC entry (ME) comprises one MTR entry and one or more MDR entries that hold the MOPs of the ME. The MDR entries of the ME have a program order. Each MDR entry holds MOPs and a next MDR entry pointer. Each MTR entry holds initial MDR entry pointers and specifies the number of the MDR entries of the ME. During ME allocation, the MOC populates the MDR entry pointers to point to the MDR entries based on the program order. In response to an access that hits upon an MTR entry, the MOC fetches the MDR entries according to the program order initially using the initial pointers and subsequently using the next pointers.

Abstract: A microprocessor includes execution units that execute macro-operations (MOPs), a decode unit that decodes architectural instructions into MOPs, an instruction fetch unit (IFU) having an instruction cache that caches architectural instructions and a macro-operation cache (MOC) that caches MOPs into which the architectural instructions are decoded. A prediction unit (PRU) predicts a series of fetch blocks (FBs) in a program instruction stream to be fetched by the IFU from the MOC if hit or from the instruction cache otherwise. A branch target buffer (BTB) caches information about previously fetched and decoded FBs. A counter of each BTB entry is incremented when the entry predicts the associated FB is present again. For each FB in the series, the PRU indicates whether the counter has exceeded a threshold for use deciding whether to allocate the MOPs into the MOC in response to an instance of decoding the instructions into the MOPs.

Abstract: A microprocessor includes execution units that execute macro-operations (MOPs), a decode unit that decodes architectural instructions into MOPs, an instruction fetch unit (IFU) having an instruction cache that caches architectural instructions and a macro-operation cache (MOC) that caches MOPs into which the architectural instructions are decoded. A prediction unit (PRU) predicts a series of fetch blocks (FBs) in a program instruction stream to be fetched by the IFU from the MOC if hit or from the instruction cache otherwise. A branch target buffer (BTB) caches information about previously fetched and decoded FBs. A counter of each BTB entry is incremented when the entry predicts the associated FB is present again. For each FB in the series, the PRU indicates whether the counter has exceeded a threshold for use deciding whether to allocate the MOPs into the MOC in response to an instance of decoding the instructions into the MOPs.

Abstract: A microprocessor includes a macro-op (MOP) cache (MOC) comprising a set-associative MOC tag RAM (MTR) and a MOC data RAM (MDR) managed as a pool of MDR entries. A MOC entry (ME) comprises one MTR entry and one or more MDR entries that hold the MOPs of the ME. The MDR entries of the ME have a program order. Each MDR entry holds MOPs and a next MDR entry pointer. Each MTR entry holds initial MDR entry pointers and specifies the number of the MDR entries of the ME. During ME allocation, the MOC populates the MDR entry pointers to point to the MDR entries based on the program order. In response to an access that hits upon an MTR entry, the MOC fetches the MDR entries according to the program order initially using the initial pointers and subsequently using the next pointers.

Abstract: A microprocessor that includes a prediction unit (PRU) comprising a branch target buffer (BTB). Each BTB entry is associated with a fetch block (FBlk) (sequential set of instructions starting at a fetch address (FA)) having a length (no longer than a predetermined maximum length) and termination type. The termination type is from a list comprising: a sequential termination type indicating that a FA of a next FBlk in program order is sequential to a last instruction of the FBlk, and one or more non-sequential termination types. The PRU uses the FA of a current FBlk to generate a current BTB lookup value, looks up the current BTB lookup value, and in response to a miss, predicts the current FBlk has the predetermined maximum length and sequential termination type. An instruction fetch unit uses the current FA and predicted predetermined maximum length to fetch the current FBlk from an instruction cache.

Abstract: A prediction unit includes a first predictor that provides an output comprising a hashed fetch address of a current fetch block in response to an input. The first predictor input comprises a hashed fetch address of a previous fetch block that immediately precedes the current fetch block in program execution order. A second predictor provides an output comprising a fetch address of a next fetch block that immediately succeeds the current fetch block in program execution order in response to an input. The second predictor input comprises the hashed fetch address of the current fetch block output by the first predictor.

Abstract: A microprocessor that includes a prediction unit (PRU) comprising a branch target buffer (BTB). Each BTB entry is associated with a fetch block (FBlk) (sequential set of instructions starting at a fetch address (FA)) having a length (no longer than a predetermined maximum length) and termination type. The termination type is from a list comprising: a sequential termination type indicating that a FA of a next FBlk in program order is sequential to a last instruction of the FBlk, and one or more non-sequential termination types. The PRU uses the FA of a current FBlk to generate a current BTB lookup value, looks up the current BTB lookup value, and in response to a miss, predicts the current FBlk has the predetermined maximum length and sequential termination type. An instruction fetch unit uses the current FA and predicted predetermined maximum length to fetch the current FBlk from an instruction cache.

Abstract: A prediction unit includes a single-cycle predictor (SCP) configured to provide a series of outputs associated with a respective series of fetch blocks on a first respective series of clock cycles and a fetch block prediction unit (FBPU) configured to use the series of SCP outputs to provide, on a second respective series of clock cycles, a respective series of fetch block descriptors that describe the respective series of fetch blocks. The fetch block descriptors are useable by an instruction fetch unit to fetch the series of fetch blocks from an instruction cache. The second respective series of clock cycles follows the first respective series of clock cycles in a pipelined fashion by a latency of the FBPU.

Abstract: An instruction fetch pipeline includes first, second, and third sub-pipelines that respectively include: a TLB that receives a fetch virtual address, a tag random access memory (RAM) of a physically-indexed physically-tagged set associative instruction cache that receives a predicted set index, and a data RAM that receives the predicted set index and a predicted way number that specifies a way of the entry from which a block of instructions was previously fetched. The predicted set index specifies the instruction cache set that includes the entry. The three sub-pipelines respectively initiate in parallel: a TLB access using the fetch virtual address to obtain a translation thereof into a fetch physical address that includes a tag, a tag RAM access using the predicted set index to read a set of tags, and a data RAM access using the predicted set index and the predicted way number to fetch the block of instructions.

Abstract: A dynamically-foldable instruction fetch pipeline receives a first fetch request that includes a fetch virtual address and includes first, second and third sub-pipelines that respectively include a translation lookaside buffer (TLB) that translates the fetch virtual address into a fetch physical address, a tag random access memory (RAM) of a physically-indexed physically-tagged set associative instruction cache that receives a set index that selects a set of tag RAM tags for comparison with a tag portion of the fetch physical address to determine a correct way of the instruction cache, and a data RAM of the instruction cache that receives the set index and a way number that together specify a data RAM entry from which to fetch an instruction block. When a control signal indicates a folded mode, the sub-pipelines operate in a parallel manner. When the control signal indicates a unfolded mode, the sub-pipelines operate in a sequential manner.

Abstract: A microprocessor includes a branch target buffer (BTB). Each BTB entry holds a tag based on at least a portion of a virtual address of a block of instructions previously fetched from a physically-indexed physically-tagged set associative instruction cache using a physical address that is a translation of the virtual address, a translated address bit portion of a set index of an instruction cache entry from which the instruction block was previously fetched, and a way number of the instruction cache entry from which the instruction block was previously fetched. In response to a BTB hit based on a fetch virtual address, the BTB provides a translated address bit portion of a predicted set index that is the translated address bit portion of the set index from the hit on BTB entry and a predicted way number that is the way number from the hit on BTB entry.

Abstract: An instruction fetch pipeline includes first, second, and third sub-pipelines that respectively include: a TLB that receives a fetch virtual address, a tag random access memory (RAM) of a physically-indexed physically-tagged set associative instruction cache that receives a predicted set index, and a data RAM that receives the predicted set index and a predicted way number that specifies a way of the entry from which a block of instructions was previously fetched. The predicted set index specifies the instruction cache set that includes the entry. The three sub-pipelines respectively initiate in parallel: a TLB access using the fetch virtual address to obtain a translation thereof into a fetch physical address that includes a tag, a tag RAM access using the predicted set index to read a set of tags, and a data RAM access using the predicted set index and the predicted way number to fetch the block of instructions.

Abstract: A prediction unit includes a first predictor that provides an output comprising a hashed fetch address of a current fetch block in response to an input. The first predictor input comprises a hashed fetch address of a previous fetch block that immediately precedes the current fetch block in program execution order. A second predictor provides an output comprising a fetch address of a next fetch block that immediately succeeds the current fetch block in program execution order in response to an input. The second predictor input comprises the hashed fetch address of the current fetch block output by the first predictor.

Abstract: A prediction unit includes a single-cycle predictor (SCP) configured to provide a series of outputs associated with a respective series of fetch blocks on a first respective series of clock cycles and a fetch block prediction unit (FBPU) configured to use the series of SCP outputs to provide, on a second respective series of clock cycles, a respective series of fetch block descriptors that describe the respective series of fetch blocks. The fetch block descriptors are useable by an instruction fetch unit to fetch the series of fetch blocks from an instruction cache. The second respective series of clock cycles follows the first respective series of clock cycles in a pipelined fashion by a latency of the FBPU.

Abstract: An instruction fetch pipeline includes first, second, and third sub-pipelines that respectively include: a TLB that receives a fetch virtual address, a tag random access memory (RAM) of a physically-indexed physically-tagged set associative instruction cache that receives a predicted set index, and a data RAM that receives the predicted set index and a predicted way number that specifies a way of the entry from which a block of instructions was previously fetched. The predicted set index specifies the instruction cache set that includes the entry. The three sub-pipelines respectively initiate in parallel: a TLB access using the fetch virtual address to obtain a translation thereof into a fetch physical address that includes a tag, a tag RAM access using the predicted set index to read a set of tags, and a data RAM access using the predicted set index and the predicted way number to fetch the block of instructions.

Abstract: A microprocessor includes a branch target buffer (BTB). Each BTB entry holds a tag based on at least a portion of a virtual address of a block of instructions previously fetched from a physically-indexed physically-tagged set associative instruction cache using a physical address that is a translation of the virtual address, a translated address bit portion of a set index of an instruction cache entry from which the instruction block was previously fetched, and a way number of the instruction cache entry from which the instruction block was previously fetched. In response to a BTB hit based on a fetch virtual address, the BTB provides a translated address bit portion of a predicted set index that is the translated address bit portion of the set index from the hit on BTB entry and a predicted way number that is the way number from the hit on BTB entry.

Abstract: A dynamically-foldable instruction fetch pipeline receives a first fetch request that includes a fetch virtual address and includes first, second and third sub-pipelines that respectively include a translation lookaside buffer (TLB) that translates the fetch virtual address into a fetch physical address, a tag random access memory (RAM) of a physically-indexed physically-tagged set associative instruction cache that receives a set index that selects a set of tag RAM tags for comparison with a tag portion of the fetch physical address to determine a correct way of the instruction cache, and a data RAM of the instruction cache that receives the set index and a way number that together specify a data RAM entry from which to fetch an instruction block. When a control signal indicates a folded mode, the sub-pipelines operate in a parallel manner. When the control signal indicates a unfolded mode, the sub-pipelines operate in a sequential manner.

Abstract: An instruction fetch pipeline includes first, second, and third sub-pipelines that respectively include: a TLB that receives a fetch virtual address, a tag random access memory (RAM) of a physically-indexed physically-tagged set associative instruction cache that receives a predicted set index, and a data RAM that receives the predicted set index and a predicted way number that specifies a way of the entry from which a block of instructions was previously fetched. The predicted set index specifies the instruction cache set that includes the entry. The three sub-pipelines respectively initiate in parallel: a TLB access using the fetch virtual address to obtain a translation thereof into a fetch physical address that includes a tag, a tag RAM access using the predicted set index to read a set of tags, and a data RAM access using the predicted set index and the predicted way number to fetch the block of instructions.

Abstract: A predictor includes a memory having a plurality of entries. Each entry includes a prediction of a hash of a next fetch address produced by a fetch block J of a series of successive fetch blocks in program execution order and a branch direction produced by the fetch block J. An input selects an entry for provision on the output. The output is fed back to the input such that the output provides the prediction of the hash of the next fetch address and the branch direction produced by each fetch block over a series of successive clock cycles. The hash of the next fetch address is insufficient for use by an instruction fetch unit to fetch from an instruction cache a fetch block J+1, whereas the next fetch address itself is sufficient for use by the instruction fetch unit to fetch from the instruction cache the fetch block J+1.

Abstract: A microprocessor includes a prediction unit pipeline having a first stage that makes first predictions at a rate of one per clock cycle. Each first prediction comprises a hash of a fetch address of a current fetch block and branch history update information produced by a previous fetch block immediately preceding the current fetch block. Second one or more stages, following the first stage, with a latency of N (at least one) clock cycles, use the first predictions to make second predictions at a rate of one per clock cycle. Each second prediction includes a fetch address of a next fetch block immediately succeeding the current fetch block and branch history update information produced by the current fetch block. For each second prediction of the second predictions, logic uses the second prediction to check whether the first prediction made N?1 clock cycles earlier than the second prediction is a mis-prediction.