Abstract: An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing characteristics. To determine those timing characteristics, each curve data set identifies at least one base curve (in the base curve database) as well as a starting current, a peak current, a peak voltage, and a peak time. In one embodiment, each base curve can be normalized. The base curve(s), the starting current, peak current, peak voltage, and peak time can accurately model the functioning of the IC device, e.g. represented by an I(V) curve.

Abstract: An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing characteristics. To determine those timing characteristics, each curve data set identifies at least one base curve (in the base curve database) as well as a starting current, a peak current, a peak voltage, and a peak time. In one embodiment, each base curve can be normalized. The base curve(s), the starting current, peak current, peak voltage, and peak time can accurately model the functioning of the IC device, e.g. represented by an I(V) curve.

Abstract: An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing characteristics. To determine those timing characteristics, each curve data set identifies at least one base curve (in the base curve database) as well as a starting current, a peak current, a peak voltage, and a peak time. In one embodiment, each base curve can be normalized. The base curve(s), the starting current, peak current, peak voltage, and peak time can accurately model the functioning of the IC device, e.g. represented by an I(V) curve.

Abstract: A method is presented for generating a timing model for a logic cell. Output load indices (Load1, Load2, . . . ,Loadm) are selected which specify output load for the first logic cell. Input ramp indices (IR1, IR2, . . . ,IRn) are selected which specify input ramp for the first logic cell. Baseline output ramp values (ORbl [j,k]) are generated for each output load index (Loadj) and input ramp index (IRk) pair. In order to take into account process, power and temperature variations, scaling factors are used to scale the indices. For example these scaling factors can be utilized for many different logic cells in a cell library. In one embodiment, the output load indices are scaled by a first scaling factor (&lgr;). The input ramp indices are scaled by a second scaling factor (&rgr;). Scaled output ramp values (ORscaled [j,k]) are generated for each scaled output load index and scaled input ramp index pair.

Abstract: In accordance with the preferred embodiment of the present invention, a logic cell library is built. Within the logic cell library a timing model for a first logic cell is generated. In order to generate the timing model a number of indices which specify input ramp for the first logic cell is selected. Also, a number of indices which specify output load for the first logic cell is selected. Also selected are a minimum value for the input ramp and a maximum value for the input ramp. A maximum output load for the timing model is calculated. This is done by calculating, for every input transition in the logic cell which causes an output transition, an intermediate value to be an output load value which results in the first logic cell producing an output signal to the first logic cell which has the maximum value for the input ramp when an input signal to the logic cell has the minimum value for the input ramp. The maximum output load is chosen to be a minimum of the calculated intermediate values.

Abstract: In a computer implemented circuit simulator, a method is provided for measuring energy consumption of a circuit under test during a measurement interval. The method comprises a series of computer implemented steps. A supply voltage is applied to the circuit under test. A current flowing through the circuit under test is then measured. A mirror voltage, representative of the value of the current, is generated. A capacitor is charged, with a power parameter voltage equal to the product of the supply voltage and the mirror voltage, during the measurement interval. An accumulated voltage is measured across the capacitor, wherein the accumulated voltage is representative of energy consumed by the circuit under test.

Abstract: A power usage simulator generates, for all the logic cells in a circuit cell library, a power model that characterizes a cell's power consumption behavior as a two-part, piecewise-linear function based on signal slew rates and output load. A logic simulator is modified so that for each signal transition in a specified logic circuit, the logic simulator performs a power usage computation utilizing the power usage model for all cells affected by each signal transition. The power usage value for each signal transition is posted to a power usage output data structure, with each posted power usage value having an associated time value. The posted power usage values are then analyzed by (A) accumulating the posted power usage values to provide a total power usage value, and (B) clocking the accumulation of power usage values with an end user set clock rate so as to produce a power usage profile indicating the time varying rate of power consumption during the simulation time period.

Abstract: A method determines approximate propagation delay through logic devices within a library. Each logic cell within the library is characterized at baseline conditions to obtain parameters for each logic cell which define propagation delay through each logic cell at the baseline conditions. A subset of the logic cells are characterized at conditions varying from the baseline conditions to obtain scaling parameters. The scaling parameters modify values of the parameters for all logic cells within the library in order to approximate changes in propagation delay through each logic cell resulting from changes in the baseline conditions. In the preferred embodiment, the conditions varying from the baseline conditions includes a change in at least one of operating temperature, power supply voltage and process conditions.

Abstract: A method approximates propagation delay through a logic device. Operation of the logic device is divided into a first region and a second region. A boundary between the first region and the second is based on duration of input ramp to the logic device and amount of capacitive load driven by the logic device. For example, the boundary between the first region and the second occurs where for each value of the capacitive load, an output ramp for the logic device is one half complete when the input ramp is complete. When the logic device operates in the first region, a first formula is used to obtain a first value representing delay through the logic device. The first formula varies the first value based on the duration of the input ramp to the logic device and the capacitive load driven by the logic device. When the logic device operates in the second region, a second formula is used to obtain the first value.

Abstract: A method estimates source resistance for a transistor. A substrate region under a gate for the transistor is modeled as a gate region having a uniform resistivity .rho..sub.g. A source of the transistor is modeled as a source region having a uniform resistivity .rho..sub.s1. The uniform resistivity .rho..sub.g and the uniform resistivity .rho..sub.s1 are used to calculate a first current from the source of the transistor to a drain of the transistor. The source of the transistor is then modeled as a source region having another uniform resistivity .rho..sub.s2. The uniform resistivity .rho..sub.s2, is different in value than uniform resistivity .rho..sub.s1. The uniform resistivity .rho..sub.g and the uniform resistivity .rho..sub.s2 are used to calculate a second current from the source of the transistor to a drain of the transistor. The uniform resistivity .rho..sub.s1, the uniform resistivity .rho..sub.