Abstract: The invention CONCERNS a device for reconfiguring an assembly of N basic electronic modules associated with k redundant modules comprising: N multiplexers each having a first terminal (di) capable of being connected to k+1 second terminals connected to the k+1 input/output terminals of a sequenced group of modules consisting of a basic module (Ui) and k other modules; N+k triggers (Fi) indicating a good or faulty condition of one of the N+k modules; and logic means associated with each multiplexer of rank j, where j is an integer ranging between 0 and N, to determine the number of triggers of rank 0 to j indicating a faulty condition, to determine the number of modules of the sequenced group associated with the module of rank j, to be counted to find a number of good modules equal to the first number, and to convert the first terminal of the multiplexer to its second terminal of rank equal to the second number.

Abstract: A device for reconfiguring faults in a circuit comprised of several units and comprising storage means for storing the fault locations, connection/disconnection means for disconnecting faulty units and connecting in their place fault-free units, and means for generating control signals of the connection/disconnection means, responding to the content of the storage means. According to this method, each unit is divided into several portions; in a test phase, fault tests are carried out for the different units, and the test results of the different portions of the units are stored in the storage means; and in a use phase aiming at the use of given unit portions, said control signals are determined by the content of the storage means corresponding to these unit portions.

Abstract: A programmable built in self test, BIST, system for testing a memory, comprises an instruction register (1) formed in the same chip as the memory; an external circuit (101) for loading directly or indirectly the register by successive instructions, each instruction comprising at least one address control field (u/d, @mode), a first number (m) of operation fields (O0-Om-1), a number-of-operations field (NO) specifying a second number t+1, with t+1≦m; a circuit (73) controlled by the address control field to determine successive addresses; and a cycle controller (32, 42-45) for executing, for each successive address, the second number (t+1) of successive operations, each of which is determined by one of the t+1 first operation fields.

Abstract: The present invention relates to a fail-safe control interface including branches for providing signals having a safe state or a non-safe state. Each branch comprises inputs for receiving at least two binary control signals (Si, Si*); a source of a non-safe state (Fe) connectable through a basic chain of elements (14, 15) to an output (Oi) when the control signals realize a predetermined combination; a concurrent checker (17) providing an error detection signal (g1, g2) if the inputs of a pair of its inputs are at predetermined states; and means (14*) for providing a first input of said pair of inputs with a signal corresponding to the state of said output and the second input of said pair of inputs with a signal corresponding to the output of a duplicate chain of the basic chain, this duplicate chain reacting like the basic chain in response to the control signals.

Abstract: To carry out a transparent test of integrated circuits, all of the state registers and input/output registers that determine the applications' execution context are included into circular scan paths having the output of the last stage connected to the input of the first stage. Before the test, the contents of the registers are shifted via the scan path into a RAM. After the test, the saved contents of the registers are reloaded from the RAM to the registers via the scan path.

Abstract: A data processing system wherein data are parity encoded for failure checking includes a logic operator generating predetermined signals responsive to input signals via first signal paths including results and carry signals, and a complement generator for generating complements of the predetermined signals responsive to the input signals received through second signal paths which are distinct from the first signal paths. In addition, the data processing system includes a double-rail checker receiving the predetermined signals from the logic operator and the complements from the generating means and for checking the logic operator responsive to the predetermined signals and the compliments and producing an output bit. The data processing system also includes a parity predictor for predicting and generating a parity bit of the results of the logic operator responsive to the output bit of the double-rail checker.