Abstract: A secure system configured to perform operations on data can include a plurality of N look-up-table fabric modules each operatively coupled to a respective column of M rows of data included in an input state matrix having N columns and M rows and a processor circuit operatively coupled to the plurality of N look-up-table fabric modules, the processor circuit configured to provide unencrypted data to the plurality of N look-up-table fabric modules for encryption and configured to provide encrypted data to the plurality of N look-up-table fabric modules for decryption.

Abstract: An electrical circuit is disclosed that comprises plurality of tunneling field-effect transistors (TFETs) arranged in a diffusion network matrix having a plurality of nodes wherein, for each of the TFETs that is not on an end of the matrix, a drain of the TFET is electrically coupled with the source of at least one of the other TFETs at a node of the matrix and a source of the TFET is electrically coupled with the drain of at least one of the other TFETs at another node of the matrix. The electrical circuit further comprises a plurality of capacitors, wherein a respective one of the plurality of capacitors is electrically coupled with each node that includes the source of at least one TFET and the drain of at least one TFET. The TFETs may be symmetrical graphene-insulator-graphene field-effect transistors (SymFETs), for example.

Abstract: Various processor architectures for mixed signal computation exploit the unique characteristics of advanced CMOS technologies, such as fin-based, multi-gate field effect transistors, and/or emerging technologies such as tunnel field effect transistors (TFETs). The example processors disclosed herein are cellular neural network (CNN)-inspired and eliminate the need for voltage controlled current sources (VCCSs), which have previously been utilized to realize feedback and feed-forward templates in CNNs and are the dominant source of power consumption in a CNN array. The example processors replace VCCSs with comparators, which can be efficiently realized with TFETs given their high intrinsic gain. Power efficiencies are in the order of 10,000 giga-operations per second per Watt (GOPS/W), which represents an improvement of more than ten times over state-of-the-art architectures seeking to accomplish similar information processing tasks.

Abstract: An electrical circuit is disclosed that comprises plurality of tunneling field-effect transistors (TFETs) arranged in a diffusion network matrix having a plurality of nodes wherein, for each of the TFETs that is not on an end of the matrix, a drain of the TFET is electrically coupled with the source of at least one of the other TFETs at a node of the matrix and a source of the TFET is electrically coupled with the drain of at least one of the other TFETs at another node of the matrix. The electrical circuit further comprises a plurality of capacitors, wherein a respective one of the plurality of capacitors is electrically coupled with each node that includes the source of at least one TFET and the drain of at least one TFET. The TFETs may be symmetrical graphene-insulator-graphene field-effect transistors (SymFETs), for example.

Abstract: Various processor architectures for mixed signal computation exploit the unique characteristics of advanced CMOS technologies, such as fin-based, multi-gate field effect transistors, and/or emerging technologies such as tunnel field effect transistors (TFETs). The example processors disclosed herein are cellular neural network (CNN)-inspired and eliminate the need for voltage controlled current sources (VCCSs), which have previously been utilized to realize feedback and feed-forward templates in CNNs and are the dominant source of power consumption in a CNN array. The example processors replace VCCSs with comparators, which can be efficiently realized with TFETs given their high intrinsic gain. Power efficiencies are in the order of 10,000 giga-operations per second per Watt (GOPS/W), which represents an improvement of more than ten times over state-of-the-art architectures seeking to accomplish similar information processing tasks.

Abstract: A Boolean gate includes at least one symmetric tunneling field-effect transistor (SymFET) for low-power information processing. SymFETs are ideal for applications that demand low power and have moderate speed requirements, and demonstrate better dynamic energy efficiency than CMOS circuits. Negative differential resistance (NDR) behavior of SymFETs leads to hysteresis in inverters and buffers, and can be used to build simple Schmitt-triggers. Further, pseudo-SymFET loads may be utilized in circuits similar to all-n-type or dynamic logic. For example, latches and flip-flops as well as NAND, NOR, IMPLY, and MAJORITY gates may employ SymFETs. Such SymFET-based devices require fewer transistors than static CMOS-based designs.

Abstract: A Boolean gate includes at least one symmetric tunneling field-effect transistor (SymFET) for low-power information processing. SymFETs are ideal for applications that demand low power and have moderate speed requirements, and demonstrate better dynamic energy efficiency than CMOS circuits. Negative differential resistance (NDR) behavior of SymFETs leads to hysteresis in inverters and buffers, and can be used to build simple Schmitt-triggers. Further, pseudo-SymFET loads may be utilized in circuits similar to all-n-type or dynamic logic. For example, latches and flip-flops as well as NAND, NOR, IMPLY, and MAJORITY gates may employ SymFETs. Such SymFET-based devices require fewer transistors than static CMOS-based designs.