Patents by Inventor Michael Nishimura

Michael Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11067710
    Abstract: A system for monitoring ionizing radiation in a target area, the system may include a first plurality of consumable nodes deployable within the target area to be exposed to the ionizing radiation. Each consumable node may be progressively damageable over a monitoring time as a result of exposure to the ionizing radiation. A base station may be operable to detect an amount of radiation damage sustained by the consumable nodes and to determine a dosage of ionizing radiation received by any one of the consumable nodes based on a pre-determined correlation between the dosage of ionizing radiation and the amount of radiation damage sustained by the consumable node.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 20, 2021
    Assignee: Atomic Energy Of Canada Limited / Energie Atomique Du Canada Limitee
    Inventors: Yu Liu, Liqian Li, Karen Dawn Collins, Michael Nishimura
  • Publication number: 20190369273
    Abstract: A system for monitoring ionizing radiation in a target area, the system may include a first plurality of consumable nodes deployable within the target area to be exposed to the ionizing radiation. Each consumable node may be progressively damageable over a monitoring time as a result of exposure to the ionizing radiation. A base station may be operable to detect an amount of radiation damage sustained by the consumable nodes and to determine a dosage of ionizing radiation received by any one of the consumable nodes based on a pre-determined correlation between the dosage of ionizing radiation and the amount of radiation damage sustained by the consumable node.
    Type: Application
    Filed: October 31, 2017
    Publication date: December 5, 2019
    Inventors: Yu Liu, Liqian Li, Karen Dawn Collins, Michael Nishimura
  • Patent number: 7362702
    Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: April 22, 2008
    Assignee: QLOGIC, Corporation
    Inventors: William C. Terrell, Tracy Edmonds, Wayland Joeng, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
  • Publication number: 20080008202
    Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a viral entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.
    Type: Application
    Filed: September 24, 2007
    Publication date: January 10, 2008
    Inventors: William Terrell, Tracy Edmonds, Wayland Jeong, Eric Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
  • Patent number: 7292567
    Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: November 6, 2007
    Assignee: QLogic Corporation
    Inventors: William C. Terrell, Tracy Edmonds, Wayland Joeng, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
  • Publication number: 20070183421
    Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.
    Type: Application
    Filed: March 30, 2007
    Publication date: August 9, 2007
    Inventors: William Terrell, Tracy Edmonds, Wayland Jeong, Eric Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
  • Patent number: 7200144
    Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: April 3, 2007
    Assignee: Qlogic, Corp.
    Inventors: William C. Terrell, Tracy Edmonds, Wayland Joeng, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
  • Publication number: 20030210686
    Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame"s destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.
    Type: Application
    Filed: October 18, 2001
    Publication date: November 13, 2003
    Applicant: Troika Networds, Inc.
    Inventors: William Terrell , Wayland Jeong , Haun Muliadi , Norman Chan , Rexford Hill , Michael Nishimura , Stephen How , Eric Peterson , Tracy Edmond
  • Publication number: 20030189936
    Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.
    Type: Application
    Filed: October 31, 2002
    Publication date: October 9, 2003
    Inventors: William C. Terrell, Tracy Edmonds, Wayland Jeong, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
  • Publication number: 20030189930
    Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.
    Type: Application
    Filed: October 29, 2002
    Publication date: October 9, 2003
    Inventors: William C. Terrell, Tracy Edmonds, Wayland Jeong, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
  • Publication number: 20030191857
    Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.
    Type: Application
    Filed: October 30, 2002
    Publication date: October 9, 2003
    Inventors: William C. Terrell, Tracy Edmonds, Wayland Jeong, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
  • Patent number: 5830755
    Abstract: The present invention provides nucleic acid sequences for T-cell receptors which recognize tumor associated antigens. In particular, T-cell receptors which recognize melanoma antigens. This invention also provides T-cells expressing the antigen specific T-cell receptors. In addition, this invention provides stem cells expressing the antigen specific T-cell receptors or chimeric receptors. This invention further relates to therapeutic and diagnostic compositions and methods employing the T-cell receptors and chimeric receptors provided herein.
    Type: Grant
    Filed: March 27, 1995
    Date of Patent: November 3, 1998
    Assignee: The United States of America as represented by the Secretary of the Department of Health and Human Services
    Inventors: Michael Nishimura, Steven A. Rosenberg