Abstract: An insulating container having a base and a lid is provided. The lid may be rotatable about a hinge from a closed configuration to an open configuration and may be secured, via one or more latching devices, in the closed configuration. In some examples, the insulating container further includes a pull handle assembly with a telescopic three-stage arm configuration defined by a stowed configuration, a partially extended configuration, and a fully extended configuration. In other examples, the insulating container further includes a wheel assembly with a pair of wheels mounted with one or two axles, and further including a wheel grommet for absorbing shock and cushioning the axle. In still other examples, the insulating container further includes a drain plug assembly on the rear sidewall adjacent to the bottom portion of the base, the drain plug assembly comprising a main tube that cooperatively engages with an outer tube with a plurality of ratchet teeth that engage one or more ratchet keys on the main tube.

Abstract: An RTL hardware description language simulation accelerator and circuit emulator which operates on data driven asynchronous completion handshaking principles. Deploying Muller C elements to control latches, the system does not depend on externally provided clocks or internal timing circuits with delay logic or clock generators. Each levelized domain of logic signals a successor level to begin execution of instructions with a level complete message produced when all its input operands have produced a completion message. Each predecessor stage holds back data production until the successor stage is ready. Each levelized data-driven asynchronous domain evaluation processor is self-timed receiving completion messages from its predecessors, and sending completion messages to its successors.

Abstract: A scalable system for verifying electronic circuit designs in anticipation of fabrication by compiling a hardware description to instructions for canvassing processors and instructions for circuit evaluation processors which are scalably interconnected to provide simulation and emulation, having deterministically scheduled transfer of circuit signal values among the large number of circuit evaluation processors.

Abstract: A logic simulation acceleration processor optimized for multi-value logic level simulation of electronic systems described in hardware description languages.

Abstract: Systems and methods for distributing, obtaining and using digital media files are disclosed. An exemplary method for distributing media files may include receiving a digital media file from a media file server. A plurality of digital media files are stored on the file server. In addition, a plurality of other media vending devices are also in electronic communication with the media file server. A request may then be received to transmit a copy of the digital media file to a portable electronic device. License information uniquely associated with the copy of the digital media file may then be determined. The copy of the digital media file and the license information may then be transmitted to the portable electronic device.

Abstract: Systems and methods for distributing, obtaining and using digital media files are disclosed. An exemplary method for distributing media files may include receiving a digital media file from a media file server. A plurality of digital media files are stored on the file server. In addition, a plurality of other media vending devices are also in electronic communication with the media file server. A request may then be received to transmit a copy of the digital media file to a portable electronic device. License information uniquely associated with the copy of the digital media file may then be determined. The copy of the digital media file and the license information may then be transmitted to the portable electronic device.

Abstract: Systems and methods for distributing, obtaining and using digital media files are disclosed. An exemplary method for distributing media files may include receiving a digital media file from a media file server. A plurality of digital media files are stored on the file server. In addition, a plurality of other media vending devices are also in electronic communication with the media file server. A request may then be received to transmit a copy of the digital media file to a portable electronic device. License information uniquely associated with the copy of the digital media file may then be determined. The copy of the digital media file and the license information may then be transmitted to the portable electronic device.

Abstract: Systems and methods for distributing, obtaining and using digital media files are disclosed. An exemplary method for distributing media files may include receiving a digital media file from a media file server. A plurality of digital media files are stored on the file server. In addition, a plurality of other media vending devices are also in electronic communication with the media file server. A request may then be received to transmit a copy of the digital media file to a portable electronic device. License information uniquely associated with the copy of the digital media file may then be determined. The copy of the digital media file and the license information may then be transmitted to the portable electronic device.

Abstract: A method and apparatus for harvesting cotton, arranged for forward motion through a cotton crop comprising cotton plants having cotton bolls.

Abstract: A functional verification system suited for verifying the function of non-cycle based integrated circuits (IC) design. The IC design is divided into a plurality of combinatorial blocks connecting sequential elements. Truth tables corresponding the divided blocks are computed and stored in a memory. The output values of the IC design are determined by evaluating the blocks. The evaluation typically entails one memory access as the truth tables are pre-computed and stored in a memory storage. Accordingly the output values are computed quickly. The storage is implemented using random access memories and a XCON is designed to ensure the dependencies are preserved during the evaluations.

Abstract: Functional verification system enabling the state of difference signals to be traced. The signals represent the outputs resulting from the evaluation of combinatorial blocks and/or a plurality of state elements forming a target design. The combinatorial blocks and/or a plurality of state elements may be grouped into multiple clusters, with each cluster being identified by a cluster identifier. The tracing circuit may include a mask memory, a previous state memory, and trace controller. Each of the mask memory and the previous state memory may contain a number of locations equal to the number of clusters such that the relevant mask and previous state information may be accessed based on the cluster identifier. The trace controller receives evaluated outputs for a cluster at bit positions specified by a corresponding mask. The trace controller compares the received bits with the previous values, and generates an entry in a trace buffer to record any changes.

Abstract: A run time controller which controls the sequence of evaluations of combinatorial blocks in a functional verification system. A target design is partitioned into multiple clusters, with each cluster in turn containing multiple combinatorial blocks. Evaluation units may be designed to evaluate the combinatorial blocks in each cluster in parallel. The run time controller may contain a flow processor, a flow control memory, and a cluster control memory. The contents of cluster control memory may be configured to specify how different condition bits/registers are to be altered upon evaluation of each cluster. The flow control memory is configured with instructions to data from different sources to be sent the evaluation units. In addition, the instructions are designed to examine the status of different registers and cause the flow processor to alter the evaluation flows.

Abstract: A functional verification system suited for verifying the function of non-cycle based integrated circuits (IC) design. The IC design is divided into a plurality of combinatorial blocks connecting sequential elements. Truth tables corresponding the divided blocks are computed and stored in a memory. The output values of the IC design are determined by evaluating the blocks. The evaluation typically entails one memory access as the truth tables are pre-computed and stored in a memory storage. Accordingly the output values are computed quickly. The storage is implemented using random access memories and a XCON is designed to ensure the dependencies are preserved during the evaluations.

Abstract: A functional verification system which can be used to evaluate either cycle based designs or non-cycle based designs. A target design is partitioned into multiple clusters, with a combinatorial block in each cluster being assigned to an evaluation unit. A flow control memory stores data indicating the sequence in which the clusters are to be evaluated. The evaluation units evaluate combinatorial blocks within a cluster in parallel. A cluster control memory indicates the manner in which a register is to be modified upon the evaluation (and results) of each cluster. The instructions in the flow control memory may be designed to examine the contents of the register and evaluate the clusters in different sequences depending on the content of the register. Evaluation of a loop of a non-cycle based design can thus be terminated based on the contents of the register.

Abstract: A functional verification system which provides information as to whether a signal has reached all possible states. For example, in the case of a signal with 0 and 1 as possible states, a 2 bit variable is initialized to 00. When a value of 1 is received for the signal, the first bit is set to 1 and when a value of 0 is received for the signal, the second bit is set to 1. Accordingly, by examining the two bits, one may determine whether the signal has attained one or both of 0 and 1 states.

Abstract: A run time controller which controls the sequence of evaluations of combinatorial blocks in a functional verification system. A target design is partitioned into multiple clusters, with each cluster in turn containing multiple combinatorial blocks. Evaluation units may be designed to evaluate the combinatorial blocks in each cluster in parallel. The run time controller may contain a flow processor, a flow control memory, and a cluster control memory. The contents of cluster control memory may be configured to specify how different condition bits/registers are to be altered upon evaluation of each cluster. The flow control memory is configured with instructions to data from different sources to be sent the evaluation units. In addition, the instructions are designed to examine the status of different registers and cause the flow processor to alter the evaluation flows.

Abstract: A functional verification system which provides information as to whether a signal has reached all possible states. For example, in the case of a signal with 0 and 1 as possible states, a 2 bit variable is initialized to 00. When a value of 1 is received for the signal, the first bit is set to 1 and when a value of 0 is received for the signal, the second bit is set to 1. Accordingly, by examining the two bits, one may determine whether the signal has attained one or both of 0 and 1 states.

Abstract: Functional verification system enabling the state of difference signals to be traced. The signals represent the outputs resulting from the evaluation of combinatorial blocks and/or a plurality of state elements forming a target design. The combinatorial blocks and/or a plurality of state elements may be grouped into multiple clusters, with each cluster being identified by a cluster identifier. The tracing circuit may include a mask memory, a previous state memory, and trace controller. Each of the mask memory and the previous state memory may contain a number of locations equal to the number of clusters such that the relevant mask and previous state information may be accessed based on the cluster identifier. The trace controller receives evaluated outputs for a cluster at bit positions specified by a corresponding mask. The trace controller compares the received bits with the previous values, and generates an entry in a trace buffer to record any changes.

Abstract: A functional verification system which can be used to evaluate either cycle based designs or non-cycle based designs. A target design is partitioned into multiple clusters, with a combinatorial block in each cluster being assigned to an evaluation unit. A flow control memory stores data indicating the sequence in which the clusters are to be evaluated. The evaluation units evaluate combinatorial blocks within a cluster in parallel. A cluster control memory indicates the manner in which a register is to be modified upon the evaluation (and results) of each cluster. The instructions in the flow control memory may be designed to examine the contents of the register and evaluate the clusters in different sequences depending on the content of the register. Evaluation of a loop of a non-cycle based design can thus be terminated based on the contents of the register.

Abstract: A method and apparatus for detecting unauthorized or accidental entry of an object into a body of water is disclosed, wherein the frequency or frequency range of sound waves in a body of water generated by the entry of the object into the body of water is determined. Then the sound waves having the frequency generated in the body of water are detected and an electrical output waveform representative of the amplitude of the sound wave in the frequency is generated. The amplitude of the electrical output waveform is subsequently averaged, so that an alarm signal is generated when the amplitude of the electrical output waveform exceeds the averaged amplitude by a predetermined value in a predetermined period of time. Once the alarm signal is generated an alarm is activated.