Abstract: A camera system may include an optics stack including first and second substrates secured together in a stacking direction, one of the first and seconds substrates including an optical element, a detector on a sensor substrate, and a feature reducing an amount of light entering at an angle greater than a field of view of the camera system from reaching the detector, the feature being on another of the first and second substrates.

Abstract: A stackable chip assembly is disclosed, as are many different embodiments relating to same. The chip assembly preferably includes at least two substrates with components mounted on each. The substrates are preferably situated with respect to one another such that components on one substrate extend towards the other substrate and vice versa. The components of each substrate preferably extend between each other. In addition various connections between the substrates are disclosed, as well as methods of constructing such chip assemblies.

Abstract: A photoionization probe includes two electrodes and provides ionizable vapor in a carrier gas via a channel between the electrodes. The ionizable vapor is thereby concentrated in an aperture of the probe where it is photoionized by, for example, an ultraviolet (UV) lamp.

Abstract: Lidded chip packages are provided in which an optoelectronic device chip has microelectronic circuits exposed at a surface of the chip with a lid mounted to overlie the optoelectronic device and the microelectronic circuits. An opaque film may be attached to the lid to overlie the microelectronic circuits while exposing the optoelectronic device. Lidded chip packages are also provided in which the lid overlies an active or passive device mounted to the chip. Wiring traces may be embedded within an adhesive between the lid and the chip.

Abstract: Methods are provided for fabricating packaged chips, each packaged chip having a protective layer, e.g., a transparent lid, metallic enclosure layer, shield layer, etc., and methods are provided for manufacturing such protective layer to be incorporated into a packaged chip. Lidded chip structures, and assemblies are also provided which include lidded chips.

Abstract: Methods are provided for fabricating packaged chips having protective layers, e.g., lids or other overlying layers having transparent, partially transparent, or opaque characteristics or a combination of such characteristics. Methods are provided for fabricating the packaged chips. Lidded chip structures and assemblies including lidded chips are also provided.

Abstract: Methods are provided for making a plurality of lidded microelectronic elements. In an exemplary embodiment, a lid wafer is assembled with a device wafer. Desirably, the lid wafer is severed into a plurality of lid elements to remove portions of the lid wafer overlying contacts at a front face of the device wafer adjacent to dicing lanes of the device wafer. Thereafter, desirably, the device wafer is severed along the dicing lanes to provide a plurality of lidded microelectronic elements.

Abstract: Packaged microelectronic elements are provided. In an exemplary embodiment, a microelectronic element having a front face and a plurality of peripheral edges bounding the front face has a device region at the front face and a contact region with a plurality of exposed contacts adjacent to at least one of the peripheral edges. The packaged element may include a plurality of support walls overlying the front face of the microelectronic element such that a lid can be mounted to the support walls above the microelectronic element. For example, the lid may have an inner surface confronting the front face. In a particular embodiment, some of the contacts can be exposed beyond edges of the lid.

Abstract: A method of making chip assemblies includes providing an in-process assembly including a semiconductor wafer, a wafer compliant structure overlying a front surface of the wafer and cavities, and terminals carried on the compliant structure adjacent the cavities and electrically connected to the wafer, the cavities being substantially sealed. The method includes subdividing the in-process assembly to form individual chip assemblies, each including one or more chip regions of the wafer, a portion of the compliant structure and the terminals carried on the portion, and opening vents communicating with said cavities after said providing step.

Abstract: A compliant structure is provided on a semiconductor wafer. The compliant structure includes cavities. The compliant structure and the wafer seal the cavities during process steps used to form conductive elements on the compliant structure. After processing, vents are opened to connect the cavities to the exterior of the assembly. The vents may be formed by severing the wafer and compliant structure to form individual units, so that the severance planes intersect channels or other voids communicating with the cavities. Alternatively, the vents may be formed by forming holes in the compliant structure, or by opening bores extending through the wafer.

Abstract: A probe is locatable adjacent a selected region of a device under test (DUT), the selected region having a plurality of contacts. A generator is capable of establishing a plume of a ionized gas between the probe and the selected region of the DUT, the plume having sufficient cross-sectional area and electrical conductivity to complete an electrical connection between the probe and the plurality of contacts.

Abstract: A microelectronic device includes a chip having a front surface and a rear surface, the front surface having an active region and a plurality of contacts exposed at the front surface outside of the active region. The device further includes a lid overlying the front surface. The lid has edges bounding the lid, at least one of the edges including one or more outer portions and one or more recesses extending laterally inwardly from the outer portions, with the contacts being aligned with the recesses and exposed through them.

Abstract: There are disclosed systems and methods in which a liquid dispensing head is positioned above the contact area of the device under test (DUT). A stream of liquid is dispensed from the head such that a continuous column of liquid extends from the head to the contact area of the test device. This column of liquid completes a circuit which allows current to flow thereby allowing for current measurement.

Abstract: There present invention is directed to a system and method which a liquid dispensing head is positioned above the contact area of the device under test (DUT). Liquid droplets are dispensed form the head and these droplets are charged with an electrical charge so that when the drops form a pool of liquid on the contact area the pool is charged thereby causing current to flow in the DUT. In this manner, for example, the transistor at each pixel of an OLED can be tested. In one embodiment an inkjet head is used to dispense fluid that is subsequently charged. In still another embodiment, the inkjet head is piezoelectric.

Abstract: There is disclosed a contactless test probe using an ionized gas discharge for making electrical contact with the device under test (DUT). In one embodiment the ionized gas discharge is at or below atmospheric pressure thereby reducing the complexity of the control environment. In one embodiment, the atmospheric gas discharge, i.e. the electrical probing medium, is created and controlled by a micro-hollow cathode. In a further embodiment an extension gate is used to extend/retard the range of the high-density discharge.

Abstract: A non-contact test method and apparatus is disclosed that can be used to test OLED flat panel TFTs. An ionized gas is used to supply current to the device under test.

Abstract: Methods and apparatus for non-contact electrical probes are described. In accordance with the invention, non-contact electrical probes use negative or positive corona discharge. Non-contact electrical probes are suited for testing of OLED flat panel displays.

Abstract: Selective area stamping of optical elements may be performed to make multiple micro-optic components on one or two sides of a substrate may be fabricated using a batch process. The presence of molding material may be controlled on the substrate through the use of gaps.

Abstract: A method of monitoring fiber optic circuits. Included is manipulating a first switch between a first state, with first connection points optically linked along a first optical signal pathway and second connection points optically linked along a second optical signal pathway, and a second loopback state, with the first and second connection points of a first pair of connection locations in communication along a path along a portion of the first and second optical signal pathways. With the first switch in the first state, a third pair of connection locations are linked to the first optical pathway and the optical throughout observed. The third pair of connection locations are then linked to the second optical pathway and the optical throughout observed. These steps are repeated as long as the first and second optical pathways transmit the optical throughout normally.

Abstract: A fiber optic circuit provides signal access and monitoring. A module housing the circuit and the module is mountable to a chassis. The module housing includes mounting flanges for mounting the module to the chassis; and a plurality of exposed adapters along at least one of the front and rear faces. Each of the plurality of adapters is connectable to a fiber optic connector external to the module. The plurality of adapters define first and second transmit signal ports and first and second receive signal ports. A transmit signal pathway is between the first and second transmit signal port. A receive signal pathway is between the first and second receive signal ports.