Patents by Inventor Michael O'Neal Fox

Michael O'Neal Fox has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8751990
    Abstract: A system for determining the median of a plurality of data values comprises a plurality of field programmable gate arrays (FPGA), a plurality of inter FPGA links, an input router, a plurality of median modules, and a plurality of output transfer modules. Each FPGA includes a plurality of configurable logic elements and configurable storage elements from which the other components are formed. The inter FPGA link allows communication from one FPGA to another. The input router receives the plurality of data values and creates a plurality of data streams. The median module receives at least one data stream, increments a plurality of counters corresponding to a single data value within the range of data values, and determines the median by accumulating the contents of each counter. The output transfer module transfers the median to an external destination along with performance statistics of the determination of the median.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: June 10, 2014
    Assignee: L3 Communications Integrated Systems, L.P.
    Inventors: Matthew R. Standfield, Jim D. Allen, Juan Esteban Flores, Michael O'Neal Fox, Deepak Prasanna, Matthew P. DeLaquil
  • Patent number: 8139864
    Abstract: A system for correcting image characteristic data from a plurality of pixels comprises at least one field programmable gate array (FPGA), a lookup table, and a correction module. The FPGA may include a plurality of configurable logic elements and a plurality of configurable storage elements. The lookup table may be accessible by the FPGA and may store a plurality of correction components associated with each pixel, including a gain value, an offset value, and a bad pixel value. The correction module may be formed from the configurable logic elements and configurable storage elements and may receive the characteristic data and the correction components. The correction module may generate corrected data for each characteristic data by utilizing the gain value, the offset value, and the bad pixel value.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: March 20, 2012
    Assignee: L3 Communications Integrated Systems, L.P.
    Inventors: Matthew R. Standfield, Jim D. Allen, Michael O'Neal Fox, Deepak Prasanna, Matthew P. DeLaquil
  • Publication number: 20110010509
    Abstract: A system for sorting data and calculating statistics on large data sets with a known value range includes a memory element and a processing element configured to execute steps of the methods. Methods for sorting data include establishing an array of counters such that each counter corresponds to a value in the data set, reading the numbers and incrementing the counter corresponding to the value of each number, and listing the values in sequential order wherein each value occurs in the list according to the count of the corresponding counter. Methods for calculating statistics utilize the count stored in each counter from the sorted data and the value that corresponds thereto.
    Type: Application
    Filed: July 7, 2009
    Publication date: January 13, 2011
    Applicant: L3 Communications Integrated Systems,L.P.
    Inventors: Juan Esteban Flores, Michael O'Neal Fox, Jim D. Allen
  • Publication number: 20100161695
    Abstract: A system for determining the median of a plurality of data values comprises a plurality of field programmable gate arrays (FPGA), a plurality of inter FPGA links, an input router, a plurality of median modules, and a plurality of output transfer modules. Each FPGA includes a plurality of configurable logic elements and configurable storage elements from which the other components are formed. The inter FPGA link allows communication from one FPGA to another. The input router receives the plurality of data values and creates a plurality of data streams. The median module receives at least one data stream, increments a plurality of counters corresponding to a single data value within the range of data values, and determines the median by accumulating the contents of each counter. The output transfer module transfers the median to an external destination along with performance statistics of the determination of the median.
    Type: Application
    Filed: December 19, 2008
    Publication date: June 24, 2010
    Applicant: L3 COMMUNICATIONS INTEGRATED SYSTEMS, L.P.
    Inventors: Matthew R. Standfield, Jim D. Allen, Juan Esteban Flores, Michael O'Neal Fox, Deepak Prasanna, Matthew P. DeLaquil
  • Publication number: 20100158407
    Abstract: A system for correcting image characteristic data from a plurality of pixels comprises at least one field programmable gate array (FPGA), a lookup table, and a correction module. The FPGA may include a plurality of configurable logic elements and a plurality of configurable storage elements. The lookup table may be accessible by the FPGA and may store a plurality of correction components associated with each pixel, including a gain value, an offset value, and a bad pixel value. The correction module may be formed from the configurable logic elements and configurable storage elements and may receive the characteristic data and the correction components. The correction module may generate corrected data for each characteristic data by utilizing the gain value, the offset value, and the bad pixel value.
    Type: Application
    Filed: December 19, 2008
    Publication date: June 24, 2010
    Applicant: L3 COMMUNICATIONS INTEGRATED SYSTEMS, L.P.
    Inventors: Matthew R. Standfield, Jim D. Allen, Michael O'Neal Fox, Deepak Prasanna, Matthew P. DeLaquil