Abstract: A SAR analog-to-digital Converter (ADC) is disclosed with variable gain having a SAR capacitor array with a plurality of switched capacitors therein with varying weights and a SAR controller for sampling an input voltage thereon in a sampling phase, and redistributing the charge stored thereon in a conversion phase in accordance with a SAR conversion algorithm. A gain adjust register is provided for defining an amount of charge to be added or subtracted from the capacitor array prior to the conversion phase relative to a predetermined amount of charge. A charge control device varies the amount of charge stored in the array prior to the conversion phase in accordance with the contents of the gain adjust register such that the amount of charge redistributed during the conversion phase is adjusted.

Abstract: A SAR analog-to-digital Converter (ADC) is disclosed with variable gain having a SAR capacitor array with a plurality of switched capacitors therein with varying weights and a SAR controller for sampling an input voltage thereon in a sampling phase, and redistributing the charge stored thereon in a conversion phase in accordance with a SAR conversion algorithm. A gain adjust register is provided for defining an amount of charge to be added or subtracted from the capacitor array prior to the conversion phase relative to a predetermined amount of charge. A charge control device varies the amount of charge stored in the array prior to the conversion phase in accordance with the contents of the gain adjust register such that the amount of charge redistributed during the conversion phase is adjusted.