Abstract: A method, system and computer program product for reducing the amount of helper data that needs to be stored using two innovative techniques. The first technique uses bit-error-rate (BER)-aware lossy compression. By treating a fraction of reliable bits as unreliable, it effectively reduces the size of the reliability mask. With the view of practical costs of production-time error characterization, the second technique enables economically feasible across-temperature per-bit BER evaluation for use in a number of fuzzy extractor optimizations based on bit-selection to reduce overall BER (with or without subsequent compression) using room-temperature only production-time characterization. The technique is based on stochastic concentration theory and allows efficiently forming confidence intervals for average across-temperature BER of a selected set of bits.

Abstract: A method, system and computer program product for reducing the amount of helper data that needs to be stored using two innovative techniques. The first technique uses bit-error-rate (BER)-aware lossy compression. By treating a fraction of reliable bits as unreliable, it effectively reduces the size of the reliability mask. With the view of practical costs of production-time error characterization, the second technique enables economically feasible across-temperature per-bit BER evaluation for use in a number of fuzzy extractor optimizations based on bit-selection to reduce overall BER (with or without subsequent compression) using room-temperature only production-time characterization. The technique is based on stochastic concentration theory and allows efficiently forming confidence intervals for average across-temperature BER of a selected set of bits.

Abstract: An electronic circuit for implementing a physically unclonable function. The electronic circuit includes duplicate circuits, referred to as “circuit primitives,” that generate a first and a second output voltage based on the received input, referred to as a “challenge.” The electronic circuit further includes a comparator coupled to the circuit primitives and generates an output based on the difference between the first and second output voltages. While the circuit primitives contain duplicate circuitry, the circuit primitives may generate a different output voltage due to a particular set of transistors in the circuit primitives operating in the sub-threshold region whose gates are tied to ground and whose sub-threshold current, the magnitude of which is random based on the threshold voltage variation of the set of transistors, is used to affect the value of the output voltage.

Abstract: An electronic circuit for implementing a physically unclonable function. The electronic circuit includes duplicate circuits, referred to as “circuit primitives,” that generate a first and a second output voltage based on the received input, referred to as a “challenge.” The electronic circuit further includes a comparator coupled to the circuit primitives and generates an output based on the difference between the first and second output voltages. While the circuit primitives contain duplicate circuitry, the circuit primitives may generate a different output voltage due to a particular set of transistors in the circuit primitives operating in the sub-threshold region whose gates are tied to ground and whose sub-threshold current, the magnitude of which is random based on the threshold voltage variation of the set of transistors, is used to affect the value of the output voltage.

Abstract: Two methods for post-synthesis circuit optimization are disclosed. In both methods, the underlying variability in process parameters is captured through a robust linear program. The robust linear program is then reformulated as a second order conic program that possesses special structural properties to allow for a computationally efficient solution by using interior point optimization methods. The first method treats gate delays as uncertain quantities and obtains the optimal sizes for gates in a circuit under a probabilistically specified circuit timing target. The second method optimizes total circuit power by using a combination of dual threshold voltage assignment and gate sizing. Both circuit power and timing are treated probabilistically.

Abstract: Two methods for post-synthesis circuit optimization are disclosed. In both methods, the underlying variability in process parameters is captured through a robust linear program. The robust linear program is then reformulated as a second order conic program that possesses special structural properties to allow for a computationally efficient solution by using interior point optimization methods. The first method treats gate delays as uncertain quantities and obtains the optimal sizes for gates in a circuit under a probabilistically specified circuit timing target. The second method optimizes total circuit power by using a combination of dual threshold voltage assignment and gate sizing. Both circuit power and timing are treated probabilistically.