Abstract: Example embodiments herein disclose systems and methods for the secure cryptographic authentication of contactless cards by distributed entities. In an example embodiment, a distributed network authentication system can comprises a client node and a distributed ledger node in data communication with the client node, wherein the distributed ledger can contain a database storing a mapping. The client node can receive, from a client device, an authentication request, and responsive to the authentication request, transmit, to the distributed ledger node, a query. The distributed ledger node can receive, from the client node, the query, submit the query to the database, receive, from the database responsive to the query, an identification of at least one selected from the group of a validation node and a validation node address, and transmit, to the client node, the identification.

Abstract: Example embodiments of systems and methods for data transmission system between transmitting and receiving devices are provided. In an embodiment, each of the transmitting and receiving devices can contain a master key. The transmitting device can generate a diversified key using the master key, protect a counter value and encrypt data prior to transmitting to the receiving device, which can generate the diversified key based on the master key and can decrypt the data and validate the protected counter value using the diversified key.

Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.

Abstract: A receiver, transmitter and method for enabling a replay using a packetized link protocol are provided. In one embodiment, the method includes: (1) transmitting a stream of packets including an untagged packet and (2) using synchronized counters to determine a sequence ID of the untagged packet, which is a corrupt/lost packet that needs to be retransmitted.

Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.

Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.

Abstract: A method and apparatus using temperature margin to balance performance with power allocation. Nominal, middle and high power levels are determined for compute elements. A set of temperature thresholds are determined that drive the power allocation of the compute elements towards a balanced temperature profile. For a given workload, temperature differentials are determined for each of the compute elements relative the other compute elements, where the temperature differentials correspond to workload utilization of the compute element. If temperature overhead is available, and a compute element is below a temperature threshold, then particular compute elements are allocated power to match or drive toward the balanced temperature profile.

Abstract: A receiver, transmitter and method for enabling a replay using a packetized link protocol are provided. In one embodiment, the method includes: (1) transmitting a stream of packets including an untagged packet and (2) using synchronized counters to determine a sequence ID of the untagged packet, which is a corrupt/lost packet that needs to be retransmitted.

Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.

Abstract: A method and apparatus using temperature margin to balance performance with power allocation. Nominal, middle and high power levels are determined for compute elements. A set of temperature thresholds are determined that drive the power allocation of the compute elements towards a balanced temperature profile. For a given workload, temperature differentials are determined for each of the compute elements relative the other compute elements, where the temperature differentials correspond to workload utilization of the compute element. If temperature overhead is available, and a compute element is below a temperature threshold, then particular compute elements are allocated power to match or drive toward the balanced temperature profile.

Abstract: A method and apparatus using temperature margin to balance performance with power allocation. Nominal, middle and high power levels are determined for compute elements. A set of temperature thresholds are determined that drive the power allocation of the compute elements towards a balanced temperature profile. For a given workload, temperature differentials are determined for each of the compute elements relative the other compute elements, where the temperature differentials correspond to workload utilization of the compute element. If temperature overhead is available, and a compute element is below a temperature threshold, then particular compute elements are allocated power to match or drive toward the balanced temperature profile.

Abstract: A method and apparatus using temperature margin to balance performance with power allocation. Nominal, middle and high power levels are determined for compute elements. A set of temperature thresholds are determined that drive the power allocation of the compute elements towards a balanced temperature profile. For a given workload, temperature differentials are determined for each of the compute elements relative the other compute elements, where the temperature differentials correspond to workload utilization of the compute element. If temperature overhead is available, and a compute element is below a temperature threshold, then particular compute elements are allocated power to match or drive toward the balanced temperature profile.

Abstract: A first in, first out (FIFO) queue includes logic to provide detection of operational errors in the FIFO queue. The FIFO queue includes entries to store data written to the FIFO queue and signature bits, each signature bit corresponding to one of the entries. A test pattern and a read signature register includes a number of bits greater than a depth of the FIFO queue. A comparator compares the test pattern to the read signature register and output an error signal indicating whether the test pattern matches the read signature register.

Abstract: The present invention is comprised of an increased dietary fiber method and treatment for processed foods to add dietary fiber to processed foods, control water activity (aw) and increase the pliability of the high fiber ingredients during mixing, blending and forming operations. The method adds soluble fiber ingredients to the processed food mixtures to provide consumers with a high fiber source to meet recommended daily Adequate Intake of fiber. The method additionally reduces non-fiber carbohydrate sources and sugar alcohols providing other beneficial physiological effects and helps to control water activity by using liquid soluble fiber to bind water adding to the shelf life of the processed food products. The treatment increases the pliability of the ingredient mixtures to more thoroughly combine, mix and blend the ingredients. The treatment continues to provide increased pliability of the completed product mixture during a product forming process.

Abstract: A first in, first out (FIFO) queue includes logic to provide detection of operational errors in the FIFO queue. The FIFO queue includes entries to store data written to the FIFO queue and signature bits, each signature bit corresponding to one of the entries. A test pattern and a read signature register includes a number of bits greater than a depth of the FIFO queue. A comparator compares the test pattern to the read signature register and output an error signal indicating whether the test pattern matches the read signature register.

Abstract: The present invention is comprised of a process and multiple reduced non-fiber carbohydrate preservative treatment ingredients to control water activity (aw) in the processing of food components to extend shelf life of processed foods. The process includes formulating a specific combination of the multiple treatment ingredients to effectively produce a desired water activity (aw) level using measurements of water activity (aw) in the food components. The multiple treatment ingredients include using soluble fiber and salt to control water activity (aw) to extend shelf life and not significantly add to the non-fiber carbohydrate and calorie levels of the processed food product.

Abstract: The invention relates to mice having functionally silenced endogenous lambda (?) and kappa (?) L-chain loci, comprising antibody-producing cells in which the CH1 domain is functionally silenced, either via spontaneous processes in somatic antibody-producing cells or due to germline deletion of the CH1 domain. Mice of the invention are capable of producing H-chain-only antibody lacking a functional CH1 domain; transgenic human heavy-chain-only antibodies lacking a functional CH1 domain can be produced following insertion into the mouse of an artificial locus with human heavy chain V, D and J segments and a constant region, which is preferably a modified constant region with alterations in, around or upstream of a CH1 domain and/or removal of a CH1 domain.

Abstract: Interfaces are provided which integrate mistake-proofing concepts in a way easily understandable by the operator and easily configured by a manufacturing engineer. As mistake-proofing concepts are developed tables are populated and associated with specific assembly processes. Sensors are employed to monitor parts selection and tool usage. Sensors used for tool use and parts selection, error messages and actions to be performed or monitored are all defined and related in the tables and in turn to specific assembly orders. The tables are also populated with logic pointers, which are referenced by a Process Logic Control (PLC) unit that has been programmed to recall and carry out infinitely variable monitoring or control of the assembly process. For example when a particular order has been identified to the PLC by way of a scanned barcode or other means, a bill of material and assembly sequence is provided to the operator by appropriate means such as a CRT monitor.

Abstract: Interfaces are provided which integrate mistake-proofing concepts in a way easily understandable by the operator and easily configured by a manufacturing engineer. As mistake-proofing concepts are developed tables are populated and associated with specific assembly processes. Sensors are employed to monitor parts selection and tool usage. Sensors used for tool use and parts selection, error messages and actions to be performed or monitored are all defined and related in the tables and in turn to specific assembly orders. The tables are also populated with logic pointers, which are referenced by a Process Logic Control (PLC) unit that has been programmed to recall and carry out infinitely variable monitoring or control of the assembly process. For example when a particular order has been identified to the PLC by way of a scanned barcode or other means, a bill of material and assembly sequence is provided to the operator by appropriate means such as a CRT monitor.

Abstract: Interfaces are provided which integrate mistake-proofing concepts in a way easily understandable by the operator and easily configured by a manufacturing engineer. As mistake-proofing concepts are developed tables are populated and associated with specific assembly processes. Sensors are employed to monitor parts selection and tool usage. Sensors used for tool use and parts selection, error messages and actions to be performed or monitored are all defined and related in the tables and in turn to specific assembly orders. The tables are also populated with logic pointers, which are referenced by a Process Logic Control (PLC) unit that has been programmed to recall and carry out infinitely variable monitoring or control of the assembly process. For example when a particular order has been identified to the PLC by way of a scanned barcode or other means, a bill of material and assembly sequence is provided to the operator by appropriate means such as a CRT monitor.