Patents by Inventor Michael Ou

Michael Ou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10915467
    Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michael Ou, Jerry Wang, Meng Kun Lee
  • Publication number: 20200386692
    Abstract: A method including: obtaining a first image location for an image feature of a first image of at least part of an object surface, obtaining a second image location for an image feature in a second image of at least part of the object surface, and/or obtaining a value of the displacement between the first and second image locations, the first and second images obtained at different relative positions between an image surface of a detector and the object surface in a direction substantially parallel to the image surface and/or the object surface; and determining, by a computer system, that a physical feature is at an inspection surface or not at the inspection surface, based on an analysis of the second image location and/or the displacement value and on an anticipated image feature location of the image feature in the second image relative to the first image location.
    Type: Application
    Filed: December 19, 2017
    Publication date: December 10, 2020
    Inventors: Aage BENDIKSEN, Guobin OU, Michael Christopher KOCHANSKI, Michael Leo NELSON
  • Publication number: 20200230229
    Abstract: Embodiments of immunogens based on the HIV-1 Env fusion peptide and methods of their use and production are disclosed. Nucleic acid molecules encoding the immunogens are also provided. In several embodiments, the immunogens can be used to generate an immune response to HIV-1 Env in a subject, for example, to treat or prevent an HIV-1 infection in the subject.
    Type: Application
    Filed: October 3, 2017
    Publication date: July 23, 2020
    Applicant: THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY, DEPARTMENT OF HEALTH AND HUMAN SERVIC
    Inventors: Peter Kwong, Rui Kong, Tongqing Zhou, John Mascola, Kai Xu, Michael Gordon Joyce, Cheng Cheng, Gwo-Yu Chuang, Kevin Liu, Baoshan Zhang, Li Ou, Wing-Pui Kong, Yongping Yang
  • Patent number: 10641766
    Abstract: A universal and standalone rapid diagnostics test reader is disclosed herein that includes: a set of control electronics, an illumination component, an imaging component, a housing component, a wireless communication component, a rapid diagnostics test component, a universal rapid diagnostics test tray, wherein the tray can hold at least one rapid diagnostics test component having a shape and a size in a fixed position relative to the imaging component and the illumination component, and wherein the reader can accommodate more than one different rapid diagnostics test component, while using the same universal rapid diagnostics test tray.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: May 5, 2020
    Assignee: NowDiagnostics, Inc.
    Inventors: Onur Mudanyali, Neven Karlovac, Chieh-I Chen, Sz-Wei Wu, Yusi Ou, Yingjun Wu, Michael Williams
  • Publication number: 20200097406
    Abstract: An incoming write request received from a client is accessed. The incoming write request comprises a write command to transfer write data to a buffer memory. An initial portion of the write data is written to the buffer memory. An alignment of a final portion of the write data with respect to a memory bank width of the buffer memory is determined. The client is determined to be designated as a burst-overwrite client. In response to determining that the final portion of the write data is unaligned with the memory bank width of the buffer memory, the final portion of the write data is written to the buffer memory without preserving previously stored data based on the client being designated as a burst-overwrite client.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventor: Michael Ou
  • Publication number: 20200097202
    Abstract: A throttling value is determined according to one of multiple throttling modes. A threshold value is determined. The throttling value is compared to the threshold value. A request mask is generated based on a result of the comparison of the throttling value to the threshold value. In response to detecting the request mask, an arbitration request is masked using the request mask prior to passing the arbitration request to an arbitration component that manages access of multiple client requestors to a buffer. The arbitration request is generated in response to receiving an access request for the buffer from a client requestor of the multiple client requestors.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventor: Michael Ou
  • Publication number: 20200034588
    Abstract: A scanning apparatus and associated charging system are provided that include a universal power interface configured to receive a removable power source connected thereto where the removable power source includes a power storage unit and a charging circuit. The scanning apparatus further includes scanning circuitry that is in electrical communication with the universal power interface and is configured to scan a target. The scanning apparatus further includes a processor communicably coupled with the scanning circuitry and the universal power interface. In an instance in which the universal power interface receives the removable power source, the processor is configured to determine a type of the removable power source, select one or more parameters based on the determined type of the removable power source, and operate at least one of the scanning apparatus or the charging circuit in the removable power source based on the one or more selected parameters.
    Type: Application
    Filed: July 19, 2019
    Publication date: January 30, 2020
    Inventors: Stephen COLAVITO, Michael Vincent MIRAGLIA, Christopher ALLEN, Qinrong ZHU, HongJian JIN, Jerry QIAN, Zhongqi LIU, Oliver OU, David WILZ
  • Publication number: 20190392838
    Abstract: Systems and methods are provided that that may be implemented to extend functionality of a voice assistant and/or telecommunications software to a remote location via an endpoint device.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Inventors: Kang Ou-Yang, Michael Wu, Chung-Hung Liu, Chen Yang Chen, Hsuan-Yin Tsai
  • Publication number: 20190266110
    Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.
    Type: Application
    Filed: May 14, 2019
    Publication date: August 29, 2019
    Inventors: Michael Ou, Jerry Wang, Meng Kun Lee
  • Patent number: 10318448
    Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: June 11, 2019
    Assignee: Tidal Systems, Inc.
    Inventors: Michael Ou, Jerry Wang, Meng Kun Lee
  • Publication number: 20170364460
    Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.
    Type: Application
    Filed: August 29, 2017
    Publication date: December 21, 2017
    Inventors: Michael Ou, Jerry Wang, Meng Kun Lee
  • Patent number: 9767051
    Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: September 19, 2017
    Assignee: Tidal Systems, Inc.
    Inventors: Michael Ou, Jerry Wang, Meng Kun Lee
  • Publication number: 20150286590
    Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.
    Type: Application
    Filed: April 6, 2015
    Publication date: October 8, 2015
    Inventors: Michael Ou, Jerry Wang, Meng Kun Lee
  • Patent number: 7275120
    Abstract: An ATA/IDE host controller 100 generated from an HDL design base and a default frequency configuration script is disclosed. The controller supports ATA/IDE interface communications at a user-selected default frequency of 33, 66, 100, or 133 Mhz and at frequencies other than the default frequency using a set of programmable override timing registers 121. An internal timing control module 110 provides either the default timing parameters or the override timing parameters to the IDE host interface 102, according to the programmable override control 301.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: September 25, 2007
    Inventors: Michael Ou, Lyle E. Adams, Edward Yan
  • Patent number: 7124376
    Abstract: A pre-designed system-on-chip architecture and method includes several standard library devices, HDL source code, simulation environment and regression, synthesis scripts, software header files, software libraries, ASIC verification test suites, and makefiles. The standard library devices comprise an integrated CPU, a shared memory controller, a peripheral controller, system peripherals, a DMA controller, embedded memory, and general system control. CPU bridges are used to accommodate a variety of processor types and to insulate users from the complexities of interfacing to different kinds of processors. Such CPU bridges further allow the latest processors to be rapidly integrated into existing integration platforms and designs.
    Type: Grant
    Filed: September 17, 2001
    Date of Patent: October 17, 2006
    Assignee: Palmchip Corporation
    Inventors: S. Jauher A. Zaidi, Michael Ou, Lyle E. Adams, Stephen Chappell, Savitha Gandikota, Jon Udell, Brian Gutcher, Jef Munsil
  • Patent number: 7062587
    Abstract: The System-on-Chip apparatus and integration methodology disclosed includes a single semiconductor integrated circuit having one or more processor subsystems, one or more DMA-type peripherals, and a Memory Access Controller (MAC) on a first internal unidirectional bus. The first internal unidirectional bus controls transactions between the processor subsystem(s) and the DMA peripheral(s) using a Memory Access Controller (MAC) and unidirectional, positive-edge clocked address and transaction control signals. The first internal unidirectional bus can support burst operation, variable-speed pipelined memory transactions, and hidden arbitration. The SoC may include a second internal unidirectional bus that controls transactions between the processor subsystem(s) and non-DMA peripherals. The second internal unidirectional bus controls transactions between the processor subsystem(s) and the non-DMA peripheral(s) using unidirectional address and transaction control signals.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: June 13, 2006
    Assignee: Palmchip Corporation
    Inventors: S. Jauher A. Zaidi, Michael Ou, Lyle E. Adams, Hussam I. Ramlaoui, Billy D. Mills, Robin Bhagat
  • Publication number: 20050091432
    Abstract: The System-on-Chip (SOC) interconnection apparatus and system discloses an internal switching fabric that interconnects, via standard connection ports, one or more requestors and one or more addressable targets on a single semiconductor integrated circuit. Each target has a unique address space, may or may not have internal arbitration, and may be resident (i.e., on-chip) memory, a memory controller for resident or off-chip memory, an addressable bridge to a device, system, or subsystem, or any combination thereof. Targets and requesters are connected to the internal switching fabric using target and requestor connection ports. The internal switching fabric routes signals between requesters and targets using one or more decoder/router elements that determine which target is the designated target using an internal system memory map. Dedicated arbiters may be included for targets without internal arbitration.
    Type: Application
    Filed: October 28, 2003
    Publication date: April 28, 2005
    Applicant: Palmchip Corporation
    Inventors: Lyle Adams, Michael Ou
  • Publication number: 20040267972
    Abstract: An ATA/IDE host controller 100 generated from an HDL design base and a default frequency configuration script is disclosed. The controller supports ATA/IDE interface communications at a user-selected default frequency of 33, 66, 100, or 133 Mhz and at frequencies other than the default frequency using a set of programmable override timing registers 121. An internal timing control module 110 provides either the default timing parameters or the override timing parameters to the IDE host interface 102, according to the programmable override control 301.
    Type: Application
    Filed: May 14, 2004
    Publication date: December 30, 2004
    Applicant: Palmchip Corporation
    Inventors: Michael Ou, Lyle E. Adams, Edward Yan
  • Publication number: 20040022107
    Abstract: The System-on-Chip apparatus and integration methodology disclosed includes a single semiconductor integrated circuit having one or more processor subsystems, one or more DMA-type peripherals, and a Memory Access Controller (MAC) on a first internal unidirectional bus. The first internal unidirectional bus controls transactions between the processor subsystem(s) the MAC, and the DMA peripheral(s) using a single centralized address decoder and unidirectional, positive-edge clocked address and transaction control signals. The first internal unidirectional bus can support burst operation, variable-speed pipelined memory transactions, and hidden arbitration. The SoC may include a second internal unidirectional bus that controls transactions between the processor subsystem(s) and non-DMA peripherals. The second internal unidirectional bus controls transactions between the processor subsystem(s) and the non-DMA peripheral(s) using unidirectional address and transaction control signals.
    Type: Application
    Filed: July 28, 2003
    Publication date: February 5, 2004
    Applicant: Palmchip Corporation
    Inventors: S. Jauher A. Zaidi, Michael Ou, Lyle E. Adams, Hussam I. Ramlaoui, Billy D. Mills, Robin Bhagat
  • Patent number: 6601126
    Abstract: A system-on-chip interconnection structure and method uses unidirectional buses only, central shared memory controllers, separate interconnects for high-speed and low-speed peripherals, zero wait-state register accesses, application-specific memory map and peripherals, application-specific test methodology, allowances for cache controllers, and good fits with standard ASIC flow and tools.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: July 29, 2003
    Assignee: Palmchip Corporation
    Inventors: S. Jauher A. Zaidi, Michael Ou, Lyle E. Adams, Hussam I. Ramlaoui, Billy D. Mills, Robin Bhagat