Abstract: A throttling value is determined according to one of multiple throttling modes. A threshold value is determined. The throttling value is compared to the threshold value. A request mask is generated based on a result of the comparison of the throttling value to the threshold value. In response to detecting the request mask, an arbitration request is masked using the request mask prior to passing the arbitration request to an arbitration component that manages access of multiple client requestors to a buffer. The arbitration request is generated in response to receiving an access request for the buffer from a client requestor of the multiple client requestors.

Abstract: An incoming write request received from a client is accessed. The incoming write request comprises a write command to transfer write data to a buffer memory. An initial portion of the write data is written to the buffer memory. An alignment of a final portion of the write data with respect to a memory bank width of the buffer memory is determined. The client is determined to be designated as a burst-overwrite client. In response to determining that the final portion of the write data is unaligned with the memory bank width of the buffer memory, the final portion of the write data is written to the buffer memory without preserving previously stored data based on the client being designated as a burst-overwrite client.

Abstract: A memory slot allocation request specifying a requested number of memory slots is received from a requestor assigned to a particular class among a plurality of classes. It is determined whether allocation of the requested number of memory slots to the requestor results in satisfaction of resource allocation constraints for the plurality of classes. The resource allocation constraints include a first and second threshold for each class that determine how many memory slots can be allocated to each class. Based on determining that allocation of the requested number of memory slots to the requestor results in satisfaction of the resource allocation constraints, the memory slot allocation request is granted. The granting of the memory slot allocation request includes allocating the requested number of memory slots to the requestor.

Abstract: A memory slot allocation request specifying a requested number of memory slots is received from a requestor assigned to a particular class among a plurality of classes. It is determined whether allocation of the requested number of memory slots to the requestor results in satisfaction of resource allocation constraints for the plurality of classes. The resource allocation constraints include a first and second threshold for each class that determine how many memory slots can be allocated to each class. Based on determining that allocation of the requested number of memory slots to the requestor results in satisfaction of the resource allocation constraints, the memory slot allocation request is granted. The granting of the memory slot allocation request includes allocating the requested number of memory slots to the requestor.

Abstract: An incoming write request received from a client is accessed. The incoming write request comprises a write command to transfer write data to a buffer memory. An initial portion of the write data is written to the buffer memory. An alignment of a final portion of the write data with respect to a memory bank width of the buffer mentor is determined. The client is determined to be designated as a burst-overwrite client. In response to determining that the final portion of the write data is unaligned with the memory bank width of the buffer memory, the final portion of the write data is written to the buffer memory without preserving previously stored data based on the client being designated as a burst-overwrite client.

Abstract: A throttling value is determined according to one of multiple throttling modes. A threshold value is determined. The throttling value is compared to the threshold value. A request mask is generated based on a result of the comparison of the throttling value to the threshold value. In response to detecting the request mask, an arbitration request is masked using the request mask prior to passing the arbitration request to an arbitration component that manages access of multiple client requestors to a buffer. The arbitration request is generated in response to receiving an access request for the buffer from a client requestor of the multiple client requestors.

Abstract: An incoming write request received from a client is accessed. The incoming write request comprises a write command to transfer write data to a buffer memory. An initial portion of the write data is written to the buffer memory. An alignment of a final portion of the write data with respect to a memory bank width of the buffer memory is determined. The client is determined to be designated as a burst-overwrite client. In response to determining that the final portion of the write data is unaligned with the memory bank width of the buffer memory, the final portion of the write data is written to the buffer memory without preserving previously stored data based on the client being designated as a burst-overwrite client.

Abstract: A throttling value is determined according to one of multiple throttling modes. A threshold value is determined. The throttling value is compared to the threshold value. A request mask is generated based on a result of the comparison of the throttling value to the threshold value. In response to detecting the request mask, an arbitration request is masked using the request mask prior to passing the arbitration request to an arbitration component that manages access of multiple client requestors to a buffer. The arbitration request is generated in response to receiving an access request for the buffer from a client requestor of the multiple client requestors.

Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.

Abstract: An incoming write request received from a client is accessed. The incoming write request comprises a write command to transfer write data to a buffer memory. An initial portion of the write data is written to the buffer memory. An alignment of a final portion of the write data with respect to a memory bank width of the buffer memory is determined. The client is determined to be designated as a burst-overwrite client. In response to determining that the final portion of the write data is unaligned with the memory bank width of the buffer memory, the final portion of the write data is written to the buffer memory without preserving previously stored data based on the client being designated as a burst-overwrite client.

Abstract: A throttling value is determined according to one of multiple throttling modes. A threshold value is determined. The throttling value is compared to the threshold value. A request mask is generated based on a result of the comparison of the throttling value to the threshold value. In response to detecting the request mask, an arbitration request is masked using the request mask prior to passing the arbitration request to an arbitration component that manages access of multiple client requestors to a buffer. The arbitration request is generated in response to receiving an access request for the buffer from a client requestor of the multiple client requestors.

Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.

Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.

Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.

Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.

Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.

Abstract: An ATA/IDE host controller 100 generated from an HDL design base and a default frequency configuration script is disclosed. The controller supports ATA/IDE interface communications at a user-selected default frequency of 33, 66, 100, or 133 Mhz and at frequencies other than the default frequency using a set of programmable override timing registers 121. An internal timing control module 110 provides either the default timing parameters or the override timing parameters to the IDE host interface 102, according to the programmable override control 301.

Abstract: A pre-designed system-on-chip architecture and method includes several standard library devices, HDL source code, simulation environment and regression, synthesis scripts, software header files, software libraries, ASIC verification test suites, and makefiles. The standard library devices comprise an integrated CPU, a shared memory controller, a peripheral controller, system peripherals, a DMA controller, embedded memory, and general system control. CPU bridges are used to accommodate a variety of processor types and to insulate users from the complexities of interfacing to different kinds of processors. Such CPU bridges further allow the latest processors to be rapidly integrated into existing integration platforms and designs.

Abstract: The System-on-Chip apparatus and integration methodology disclosed includes a single semiconductor integrated circuit having one or more processor subsystems, one or more DMA-type peripherals, and a Memory Access Controller (MAC) on a first internal unidirectional bus. The first internal unidirectional bus controls transactions between the processor subsystem(s) and the DMA peripheral(s) using a Memory Access Controller (MAC) and unidirectional, positive-edge clocked address and transaction control signals. The first internal unidirectional bus can support burst operation, variable-speed pipelined memory transactions, and hidden arbitration. The SoC may include a second internal unidirectional bus that controls transactions between the processor subsystem(s) and non-DMA peripherals. The second internal unidirectional bus controls transactions between the processor subsystem(s) and the non-DMA peripheral(s) using unidirectional address and transaction control signals.

Abstract: The System-on-Chip (SOC) interconnection apparatus and system discloses an internal switching fabric that interconnects, via standard connection ports, one or more requestors and one or more addressable targets on a single semiconductor integrated circuit. Each target has a unique address space, may or may not have internal arbitration, and may be resident (i.e., on-chip) memory, a memory controller for resident or off-chip memory, an addressable bridge to a device, system, or subsystem, or any combination thereof. Targets and requesters are connected to the internal switching fabric using target and requestor connection ports. The internal switching fabric routes signals between requesters and targets using one or more decoder/router elements that determine which target is the designated target using an internal system memory map. Dedicated arbiters may be included for targets without internal arbitration.