Abstract: Systems for integrated electronic and photonic design include a graphical user interface (GUI) configured to lay out electronic and photonic design components in a design environment; a design rule checking (DRC) module configured to check design rules for electronic and photonic components according to manufacturing requirements; and a processor configured to adjust photonic components according to photonic design requirements and to reconcile conflicts between electronic and photonic components.

Abstract: Methods for integrated electronic and photonic design include laying out electronic and photonic design components in a design environment; adjusting photonic components according to photonic design requirements using a processor; checking design rules for electronic and photonic components according to manufacturing requirements; and adjusting component positioning and size to reconcile conflicts between electronic and photonic components.

Abstract: Methods for integrated electronic and photonic design include laying out electronic and photonic design components in a design environment; adjusting photonic components according to photonic design requirements using a processor; checking design rules for electronic and photonic components according to manufacturing requirements; and adjusting component positioning and size to reconcile conflicts between electronic and photonic components.

Abstract: Systems for integrated electronic and photonic design include a graphical user interface (GUI) configured to lay out electronic and photonic design components in a design environment; a design rule checking (DRC) module configured to check design rules for electronic and photonic components according to manufacturing requirements; and a processor configured to adjust photonic components according to photonic design requirements and to reconcile conflicts between electronic and photonic components.

Abstract: There is provided a method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack. Each of the two or more strata has 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements. The method includes performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack. The method further includes checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack.

Abstract: A parallel self-resetting parallel binary adder provides high speed addition and subtraction. The adder combines the advantages of a fully custom design methodology with the higher performance potential of self-resetting complementary metal oxide semiconductor (CMOS) circuits. The adder logic architecture is carry look-ahead with two bit groups and requires six rows of merge logic to calculate the carry out of the Most Significant Bit (MSB). Loading on the critical path of the adder is reduced by moving as many merge blocks as possible to later rows. This allows the fan-out per stage in the critical path to be reduced from around three to two or less. The adder utilizes a bubble pipelined circuit architecture. For the adder, a bubble pipe segment consists of a row of self-resetting circuit blocks.