Patents by Inventor Michael P. Belyansky

Michael P. Belyansky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10388766
    Abstract: A VFET device with a dual top spacer to prevent source/drain-to-gate short, and techniques for formation thereof are provided. In one aspect, a method of forming a VFET device includes: etching vertical fin channels in a substrate; forming a bottom source and drain in the substrate beneath the vertical fin channels; forming a bottom spacer on the bottom source and drain; depositing a gate dielectric and gate conductor onto the vertical fin channels; recessing the gate dielectric and gate conductor to expose tops of the vertical fin channels; selectively forming dielectric spacers on end portions of the gate dielectric and gate conductor adjacent to the tops of the vertical fin channels; depositing an encapsulation layer onto the vertical fin channels; recessing the encapsulation layer with the dielectric spacers serving as an etch stop; and forming top source and drains. A VFET device formed using the present techniques is also provided.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Shogo Mochizuki, Michael P. Belyansky, Choonghyun Lee
  • Publication number: 20190207013
    Abstract: A semiconductor structure includes a substrate, a plurality of parallel fins extending above the substrate, a plurality of gate structures perpendicular to the plurality of fins and including a plurality of sidewall spacers, and a plurality of source-drain regions intermediate the plurality of gate structures. A liner of a silicon-containing material is deposited over outer surfaces of the plurality of gate structures; over the liner, an inter-layer dielectric material is deposited. The semiconductor substrate with the deposited liner of silicon-containing material and deposited inter-layer dielectric material is annealed to at least partially consume the liner of silicon-containing material into the inter-layer dielectric material, to control residual stress such that resultant gate structures following the annealing have an aspect ratio range of 3:1 to 10:1, and are uniform in range to within seven percent of a target critical dimension.
    Type: Application
    Filed: March 4, 2019
    Publication date: July 4, 2019
    Inventors: Michael P. Belyansky, Andrew Greene, Fee Li Lie, Huimei Zhou
  • Publication number: 20190123174
    Abstract: A VFET device with a dual top spacer to prevent source/drain-to-gate short, and techniques for formation thereof are provided. In one aspect, a method of forming a VFET device includes: etching vertical fin channels in a substrate; forming a bottom source and drain in the substrate beneath the vertical fin channels; forming a bottom spacer on the bottom source and drain; depositing a gate dielectric and gate conductor onto the vertical fin channels; recessing the gate dielectric and gate conductor to expose tops of the vertical fin channels; selectively forming dielectric spacers on end portions of the gate dielectric and gate conductor adjacent to the tops of the vertical fin channels; depositing an encapsulation layer onto the vertical fin channels; recessing the encapsulation layer with the dielectric spacers serving as an etch stop; and forming top source and drains. A VFET device formed using the present techniques is also provided.
    Type: Application
    Filed: October 23, 2017
    Publication date: April 25, 2019
    Inventors: Shogo Mochizuki, Michael P. Belyansky, Choonghyun Lee
  • Patent number: 10249730
    Abstract: A semiconductor structure includes a substrate, a plurality of parallel fins extending above the substrate, a plurality of gate structures perpendicular to the plurality of fins and including a plurality of sidewall spacers, and a plurality of source-drain regions intermediate the plurality of gate structures. A liner of a silicon-containing material is deposited over outer surfaces of the plurality of gate structures; over the liner, an inter-layer dielectric material is deposited. The semiconductor substrate with the deposited liner of silicon-containing material and deposited inter-layer dielectric material is annealed to at least partially consume the liner of silicon-containing material into the inter-layer dielectric material, to control residual stress such that resultant gate structures following the annealing have an aspect ratio range of 3:1 to 10:1, and are uniform in range to within seven percent of a target critical dimension.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Belyansky, Andrew Greene, Fee Li Lie, Huimei Zhou
  • Publication number: 20190067078
    Abstract: A semiconductor structure includes a plurality of semiconductor fins on an upper surface of a semiconductor substrate. The semiconductor fins spaced apart from one another by a respective trench to define a fin pitch. A multi-layer electrical isolation region is contained in each trench. The multi-layer electrical isolation region includes an oxide layer and a protective layer. The oxide layer includes a first material on an upper surface of the semiconductor substrate. The protective layer includes a second material on an upper surface of the oxide layer. The second material is different than the first material. The first material has a first etch resistance and the second material has a second etch resistance that is greater than the first etch resistance.
    Type: Application
    Filed: August 28, 2017
    Publication date: February 28, 2019
    Inventors: Michael P. Belyansky, Richard A. Conti, Dechao Guo, Devendra K. Sadana, Jay W. Strane
  • Publication number: 20190067079
    Abstract: A semiconductor structure includes a plurality of semiconductor fins on an upper surface of a semiconductor substrate. The semiconductor fins spaced apart from one another by a respective trench to define a fin pitch. A multi-layer electrical isolation region is contained in each trench. The multi-layer electrical isolation region includes an oxide layer and a protective layer. The oxide layer includes a first material on an upper surface of the semiconductor substrate. The protective layer includes a second material on an upper surface of the oxide layer. The second material is different than the first material. The first material has a first etch resistance and the second material has a second etch resistance that is greater than the first etch resistance.
    Type: Application
    Filed: November 16, 2017
    Publication date: February 28, 2019
    Inventors: Michael P. Belyansky, Richard A. Conti, Dechao Guo, Devendra K. Sadana, Jay W. Strane
  • Patent number: 10170582
    Abstract: A method of forming a semiconductor structure includes forming a protective liner comprising a metal oxide above and in direct contact with a semiconductor substrate, a fin extending upward from the semiconductor substrate and a NON hardmask positioned on top of the fin, removing the protective liner from top surfaces of the semiconductor substrate and NON hardmask, the protective liner remaining on sidewalls of the fin and the NON hardmask, depositing a first dielectric layer, simultaneously removing top portions of the first dielectric layer and NON hardmask, the first dielectric layer remains in direct contact with a bottom portion of the protective liner and the semiconductor substrate, removing the protective liner, the removing of the protective liner creates an opening between the first dielectric layer and the bottom portion of the fin that is subsequently filled with a second dielectric layer.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Belyansky, Cheng Chi, Ekmini Anuja De Silva, Tenko Yamashita
  • Patent number: 10141188
    Abstract: A method is disclosed to prepare a substrate for photolithography. The method includes forming an underlayer over a surface of the substrate; depositing an interface hardmask layer on the underlayer using one of a vapor phase deposition process or an atomic layer deposition process; and forming a layer of extreme UV (EUV) resist on the interface hardmask layer, where the interface hardmask layer is comprised of material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer. Also disclosed is a structure configured for photolithography. The structure includes a substrate; an underlayer over a surface of the substrate; an interface hardmask layer disposed on the underlayer; and a layer of EUV resist disposed on the interface hardmask layer. The interface hardmask layer contains material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael P Belyansky, Ravi K Bonam, Anuja Desilva, Scott Halle
  • Patent number: 10134592
    Abstract: A method is disclosed to prepare a substrate for photolithography. The method includes forming an underlayer over a surface of the substrate; depositing an interface hardmask layer on the underlayer using one of a vapor phase deposition process or an atomic layer deposition process; and forming a layer of extreme UV (EUV) resist on the interface hardmask layer, where the interface hardmask layer is comprised of material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer. Also disclosed is a structure configured for photolithography. The structure includes a substrate; an underlayer over a surface of the substrate; an interface hardmask layer disposed on the underlayer; and a layer of EUV resist disposed on the interface hardmask layer. The interface hardmask layer contains material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael P Belyansky, Ravi K Bonam, Anuja Desilva, Scott Halle
  • Publication number: 20180166277
    Abstract: A method is disclosed to prepare a substrate for photolithography. The method includes forming an underlayer over a surface of the substrate; depositing an interface hardmask layer on the underlayer using one of a vapor phase deposition process or an atomic layer deposition process; and forming a layer of extreme UV (EUV) resist on the interface hardmask layer, where the interface hardmask layer is comprised of material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer. Also disclosed is a structure configured for photolithography. The structure includes a substrate; an underlayer over a surface of the substrate; an interface hardmask layer disposed on the underlayer; and a layer of EUV resist disposed on the interface hardmask layer. The interface hardmask layer contains material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer.
    Type: Application
    Filed: November 29, 2017
    Publication date: June 14, 2018
    Inventors: Michael P. Belyansky, Ravi K. Bonam, Anuja Desilva, Scott Halle
  • Publication number: 20180166278
    Abstract: A method is disclosed to prepare a substrate for photolithography. The method includes forming an underlayer over a surface of the substrate; depositing an interface hardmask layer on the underlayer using one of a vapor phase deposition process or an atomic layer deposition process; and forming a layer of extreme UV (EUV) resist on the interface hardmask layer, where the interface hardmask layer is comprised of material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer. Also disclosed is a structure configured for photolithography. The structure includes a substrate; an underlayer over a surface of the substrate; an interface hardmask layer disposed on the underlayer; and a layer of EUV resist disposed on the interface hardmask layer. The interface hardmask layer contains material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer.
    Type: Application
    Filed: November 29, 2017
    Publication date: June 14, 2018
    Inventors: Michael P. Belyansky, Ravi K. Bonam, Anuja Desilva, Scott Halle
  • Patent number: 9929012
    Abstract: A method is disclosed to prepare a substrate for photolithography. The method includes forming an underlayer over a surface of the substrate; depositing an interface hardmask layer on the underlayer using one of a vapor phase deposition process or an atomic layer deposition process; and forming a layer of extreme UV (EUV) resist on the interface hardmask layer, where the interface hardmask layer is comprised of material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer. Also disclosed is a structure configured for photolithography. The structure includes a substrate; an underlayer over a surface of the substrate; an interface hardmask layer disposed on the underlayer; and a layer of EUV resist disposed on the interface hardmask layer. The interface hardmask layer contains material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael P Belyansky, Ravi K Bonam, Anuja Desilva, Scott Halle
  • Patent number: 9613956
    Abstract: A technique relates to punchthrough stop (PTS) doping in bulk fin field effect transistors. Fins are formed on a substrate, and each pair of the fins has a fin pitch. Each of the fins has an undoped fin channel and a punchthrough stop doping region underneath the undoped fin channel. A narrow shallow trench isolation trench is formed between the fin pitch of the fins. A wide shallow trench isolation trench is formed at an outside edge of the fins. A doped layer fills the narrow shallow trench isolation trench and the wide shallow trench isolation trench. A vertical thickness of the doped layer in the narrow shallow trench isolation trench is greater than a vertical thickness of the wide shallow trench isolation trench.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael P. Belyansky, Kangguo Cheng, Ramachandra Divakaruni
  • Patent number: 9397002
    Abstract: A technique relates to punchthrough stop (PTS) doping in bulk fin field effect transistors. Fins are formed on a substrate, and each pair of the fins has a fin pitch. Each of the fins has an undoped fin channel and a punchthrough stop doping region underneath the undoped fin channel. A narrow shallow trench isolation trench is formed between the fin pitch of the fins. A wide shallow trench isolation trench is formed at an outside edge of the fins. A doped layer fills the narrow shallow trench isolation trench and the wide shallow trench isolation trench. A vertical thickness of the doped layer in the narrow shallow trench isolation trench is greater than a vertical thickness of the wide shallow trench isolation trench.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: July 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael P. Belyansky, Kangguo Cheng, Ramachandra Divakaruni
  • Publication number: 20140302685
    Abstract: A dielectric cap and related methods are disclosed. In one embodiment, the dielectric cap includes a dielectric material having an optical band gap (e.g., greater than about 3.0 electron-Volts) to substantially block ultraviolet radiation during a curing treatment, and including nitrogen with electron donor, double bond electrons. The dielectric cap exhibits a high modulus and is stable under post ULK UV curing treatments for, for example, copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability.
    Type: Application
    Filed: June 18, 2014
    Publication date: October 9, 2014
    Inventors: Michael P. Belyansky, Griselda Bonilla, Xiao Hu Liu, Son V. Nguyen, Thomas M. Shaw, Hosadurga K. Shobha, Daewon Yang
  • Publication number: 20140183720
    Abstract: Methods of manufacturing semiconductor integrated circuits having a compressive nitride layer are disclosed. In one example, a method of fabricating an integrated circuit includes depositing an aluminum layer over a semiconductor substrate, depositing a tensile silicon nitride layer or a neutral silicon nitride layer over the aluminum layer, and depositing a compressive silicon nitride layer over the tensile silicon nitride layer or the neutral silicon nitride layer. The compressive silicon nitride layer is deposited at a thickness that is at least about twice a thickness of the tensile silicon nitride layer or the neutral silicon nitride layer. Further, there is no delamination present at an interface between the aluminum layer and the tensile silicon nitride layer or the neutral silicon nitride layer, or at an interface between tensile silicon nitride layer or the neutral silicon nitride layer and the compressive nitride layer.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 3, 2014
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Scott Beasor, Jay Strane, Man Fai Ng, Brett H. Engel, Chang Yong Xiao, Michael P. Belyansky, Tsung-Liang Chen, Kyung Bum Koo
  • Patent number: 8557649
    Abstract: Methods for controlling the height of semiconductor structures are disclosed. Amorphous carbon is used as a stopping layer for controlling height variability. In one embodiment, the height of replacement metal gates for transistors is controlled. In another embodiment, the step height of a shallow trench isolation region is controlled.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: October 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Rajasekhar Venigalla, Michael Vincent Aquilino, Massud A. Aminpur, Michael P. Belyansky, Unoh Kwon, Christopher Duncan Sheraw, Daewon Yang
  • Publication number: 20130102125
    Abstract: Methods for controlling the height of semiconductor structures are disclosed. Amorphous carbon is used as a stopping layer for controlling height variability. In one embodiment, the height of replacement metal gates for transistors is controlled. In another embodiment, the step height of a shallow trench isolation region is controlled.
    Type: Application
    Filed: October 21, 2011
    Publication date: April 25, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rajasekhar Venigalla, Michael Vincent Aquilino, Massud A. Aminpur, Michael P. Belyansky, Unoh Kwon, Christopher Duncan Sheraw, Daewon Yang
  • Patent number: 8420542
    Abstract: A method of forming a reverse image pattern on a semiconductor base layer is disclosed. The method comprises depositing a transfer layer of amorphous carbon on the semiconductor base layer, depositing a resist layer on the transfer layer, creating a first pattern in the resist layer, creating the first pattern in the transfer layer, removing the resist layer, depositing a reverse mask layer, planarizing the reverse mask layer, and removing the transfer layer, thus forming a second pattern that is a reverse image of the first pattern.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: April 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Viraj Yashawant Sardesai, Michael P. Belyansky, Rajasekhar Venigalla
  • Publication number: 20120302069
    Abstract: A method of forming a reverse image pattern on a semiconductor base layer is disclosed. The method comprises depositing a transfer layer of amorphous carbon on the semiconductor base layer, depositing a resist layer on the transfer layer, creating a first pattern in the resist layer, creating the first pattern in the transfer layer, removing the resist layer, depositing a reverse mask layer, planarizing the reverse mask layer, and removing the transfer layer, thus forming a second pattern that is a reverse image of the first pattern.
    Type: Application
    Filed: May 27, 2011
    Publication date: November 29, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Viraj Yashawant Sardesai, Michael P. Belyansky, Rajasekhar Venigalla