Abstract: A multi-layer stacked semiconductor device includes a first integrated circuit device and a bonding insulator layer formed upon the first integrated circuit device. The bonding insulator layer includes an insulating material layer and an etch stop layer. The semiconductor device also includes a second integrated circuit device formed over the first integrated circuit device in a stacked configuration. The semiconductor device also includes a bonding insulator layer formed between the second integrated circuit device and the insulating material layer. The insulating material layer and the bonding insulator layer are bonded adjacent to one another.

Abstract: A stack structure that includes: a device wafer, a handler wafer, and a bonding structure disposed between the device wafer and the handler wafer, wherein one or both of the device wafer and the handler wafer have a release layer that is configured to be substantially or completely vaporized by infrared ablation when exposed to an infrared laser energy. The device wafer includes at least two consecutive layers adjacent the bonding structure that together include a plurality of fill portions that substantially or completely disable entry of the infrared laser energy into a plurality of layers of the device wafer below the two consecutive layers adjacent the bonding structure.

Abstract: A hybrid bonded semiconductor structure includes a first substrate and a second substrate each having an interface joined in a hybrid bond. Each substrate has a die portion and a crackstop structure adjacent the die portion. One or more voids in the first substrate and the second substrate are formed in or about a portion of a periphery of each crackstop structure. At least some of the one or more voids in the first substrate and the second substrate are substantially aligned to form a unified void with airgaps across the hybrid bond interface.

Abstract: Handler wafers and methods of handling a wafer include positioning a handler, which is attached to a wafer by a bonding layer that comprises a debonding layer, an optical enhancement layer, and an anti-reflection layer. The handler is debonded from the wafer using a laser that emits laser energy at a wavelength that is absorbed by the debonding layer and that is confined to the debonding layer by the optical enhancement layer, such that the material of the debonding layer ablates when exposed to the laser energy to release the wafer.

Abstract: In accordance with an embodiment of the present invention, a method and semiconductor device is described, including forming a plurality of gaps of variable size between device features, each of the gaps including vertical sidewalls perpendicular to a substrate surface and a horizontal surface parallel to the substrate surface. Spacer material is directionally deposited concurrently on the horizontal surface in each gap and in a flat area using a total flow rate of gaseous precursors that minimizes gap-loading in a smallest gap compared to the flat area such that the spacer material is deposited on the substrate surface in each gap and in the flat area to a uniform thickness.

Abstract: Embodiments of the present invention are directed to processing methods and resulting structures that leverage wafer bonding techniques to provide stacked field effect transistors (SFETs) with high-quality N/P junction isolation. In a non-limiting embodiment of the invention, a first semiconductor structure is formed on a first wafer and a second semiconductor structure is formed on a second wafer. The first wafer is positioned with respect to the second wafer such that a top surface of the first semiconductor structure is directly facing a top surface of the second semiconductor structure. A bonding layer is formed between the top surface of the first semiconductor structure and the top surface of the second semiconductor structure and the first wafer is bonded to the second wafer at a first temperature. The device is annealed at a second temperature to cure the bonding layer. The anneal temperature is greater than the bonding temperature.

Abstract: Handler wafers and methods of handling a wafer include positioning a handler, which is attached to a wafer by a bonding layer that comprises a debonding layer, an optical enhancement layer, and an anti-reflection layer. The handler is debonded from the wafer using a laser that emits laser energy at a wavelength that is absorbed by the debonding layer and that is confined to the debonding layer by the optical enhancement layer, such that the material of the debonding layer ablates when exposed to the laser energy to release the wafer.

Abstract: A semiconductor device includes a substrate with a planar top surface. At least a first gate cut stressor within a first gate cut region separates a first transistor region from a second transistor region. The first gate cut stressor is directly upon the planar top surface and applies a first tensile force perpendicular to a channel of the first transistor region and perpendicular to a channel of the second transistor region. The tensile force may improve hole and/or electron mobility within a transistor in the first transistor region and within a transistor in the second transistor region. The gate cut stressor may include a lower material within the gate cut region and an upper material upon the lower material. Alternatively, the gate cut stressor may include a liner material that lines the gate cut region and an inner material upon the liner material.

Abstract: A carrier wafer, a structure, and a method are disclosed. The carrier wafer includes a wafer layer having a first surface and a second surface opposite the first surface, a first antireflective coating (ARC) layer positioned on the first surface of the wafer layer, a second ARC layer positioned on a surface of the first ARC layer opposite the wafer layer, and a thin release layer positioned on a surface of the second ARC layer opposite the first ARC layer. The structure includes the carrier wafer and a semiconductor device substrate positioned over the thin release layer of the carrier wafer. The method includes obtaining a wafer layer, forming an ARC layer on a surface of the wafer layer, forming a second ARC layer on a surface of the first ARC layer opposite the wafer layer, and forming a thin release layer on the second ARC layer.

Abstract: A method of controlling threshold voltage shift that includes forming a first set of channel semiconductor regions on a first portion of a substrate, and forming a second set of channel semiconductor regions on a second portion of the substrate. A gate structure is formed on the first set of channel semiconductor regions and the second set of channel, wherein the gate structure extends from a first portion of the substrate over an isolation region to a second portion of the substrate. A gate cut region is formed in the gate structure over the isolation region. An oxygen scavenging metal containing layer is formed on sidewalls of the gate cut region.

Abstract: According to embodiments of the present invention, a method of forming a self-aligned contact includes depositing an etch-stop liner on a surface of a gate cap and a contact region. A dielectric oxide layer is deposited onto the etch-stop layer. The dielectric oxide layer and the etch-stop liner are removed in a region above the contact region to form a removed region. A contact is deposited in the etched region.

Abstract: According to embodiments of the present invention, a method of forming a self-aligned contact includes depositing an etch-stop liner on a surface of a gate cap and a contact region. A dielectric oxide layer is deposited onto the etch-stop layer. The dielectric oxide layer and the etch-stop liner are removed in a region above the contact region to form a removed region. A contact is deposited in the etched region.

Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.

Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.

Abstract: A VFET device with a dual top spacer to prevent source/drain-to-gate short, and techniques for formation thereof are provided. In one aspect, a method of forming a VFET device includes: etching vertical fin channels in a substrate; forming a bottom source and drain in the substrate beneath the vertical fin channels; forming a bottom spacer on the bottom source and drain; depositing a gate dielectric and gate conductor onto the vertical fin channels; recessing the gate dielectric and gate conductor to expose tops of the vertical fin channels; selectively forming dielectric spacers on end portions of the gate dielectric and gate conductor adjacent to the tops of the vertical fin channels; depositing an encapsulation layer onto the vertical fin channels; recessing the encapsulation layer with the dielectric spacers serving as an etch stop; and forming top source and drains. A VFET device formed using the present techniques is also provided.

Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.

Abstract: In accordance with an embodiment of the present invention, a method and semiconductor device is described, including forming a plurality of gaps of variable size between device features, each of the gaps including vertical sidewalls perpendicular to a substrate surface and a horizontal surface parallel to the substrate surface. Spacer material is directionally deposited concurrently on the horizontal surface in each gap and in a flat area using a total flow rate of gaseous precursors that minimizes gap-loading in a smallest gap compared to the flat area such that the spacer material is deposited on the substrate surface in each gap and in the flat area to a uniform thickness.

Abstract: In accordance with an embodiment of the present invention, a method and semiconductor device is described, including forming a plurality of gaps of variable size between device features, each of the gaps including vertical sidewalls perpendicular to a substrate surface and a horizontal surface parallel to the substrate surface. Spacer material is directionally deposited concurrently on the horizontal surface in each gap and in a flat area using a total flow rate of gaseous precursors that minimizes gap-loading in a smallest gap compared to the flat area such that the spacer material is deposited on the substrate surface in each gap and in the flat area to a uniform thickness.

Abstract: An integrated semiconductor device having a substrate and a vertical field-effect transistor (FET) disposed on the substrate. The vertical FET includes a fin and a bottom spacer. The bottom spacer further includes a first spacer layer and a second spacer layer formed on top of the first spacer layer. The bottom spacer provides for a symmetrical straight alignment at a bottom junction between the bottom spacer and the fin.

Abstract: An integrated semiconductor device having a substrate and a vertical field-effect transistor (FET) disposed on the substrate. The vertical FET includes a fin and a bottom spacer. The bottom spacer further includes a first spacer layer and a second spacer layer formed on top of the first spacer layer. The bottom spacer provides for a symmetrical straight alignment at a bottom junction between the bottom spacer and the fin.