Patents by Inventor Michael P. Chudzik
Michael P. Chudzik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9911597Abstract: A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.Type: GrantFiled: May 15, 2017Date of Patent: March 6, 2018Assignee: International Business Machines CorporationInventors: Takashi Ando, Eduard A. Cartier, Michael P. Chudzik, Aritra Dasgupta, Herbert L. Ho, Donghun Kang, Rishikesh Krishnan, Vijay Narayanan, Kern Rim
-
Patent number: 9831084Abstract: A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations.Type: GrantFiled: October 3, 2015Date of Patent: November 28, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Michael P. Chudzik, Min Dai, Martin M. Frank, David F. Hilscher, Rishikesh Krishnan, Barry P. Linder, Claude Ortolland, Joseph F. Shepard, Jr.
-
Patent number: 9793216Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.Type: GrantFiled: January 26, 2016Date of Patent: October 17, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Joyeeta Nag, Jim Shih-Chun Liang, Domingo A. Ferrer Luppi, Atsushi Ogino, Andrew H. Simon, Michael P. Chudzik
-
Publication number: 20170250073Abstract: A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.Type: ApplicationFiled: May 15, 2017Publication date: August 31, 2017Inventors: Takashi Ando, Eduard A. Cartier, Michael P. Chudzik, Aritra Dasgupta, Herbert L. Ho, Donghun Kang, Rishikesh Krishnan, Vijay Narayanan, Kern Rim
-
Publication number: 20170236780Abstract: An aspect of the disclosure is directed to a method of forming an interconnect for use in an integrated circuit. The method comprises: forming an opening in a dielectric layer on a substrate; filling the opening with a metal such that an overburden outside of the opening is created; subjecting the metal to a microwave energy dose such that atoms from the overburden migrate to within the opening; and planarizing the metal to a top surface of the opening to remove the overburden, thereby forming the interconnect.Type: ApplicationFiled: April 12, 2017Publication date: August 17, 2017Inventors: Joyeeta Nag, Shishir K. Ray, Andrew H. Simon, Oleg Gluschenkov, Siddarth A. Krishnan, Michael P. Chudzik
-
Publication number: 20170213792Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.Type: ApplicationFiled: January 26, 2016Publication date: July 27, 2017Inventors: Joyeeta Nag, Jim Shih-Chun Liang, Domingo A. Ferrer Luppi, Atsushi Ogino, Andrew H. Simon, Michael P. Chudzik
-
Publication number: 20170170077Abstract: A method of manufacturing a semiconductor structure, and the resultant structure. The method includes forming an oxide layer above a substrate. The method includes forming a metal layer above the oxide layer. The method includes forming a first capping layer above the metal layer. A material forming the first capping layer may be titanium oxide, or titanium oxynitride. The method includes annealing the semiconductor structure. Annealing the semiconductor structure may result in diffusing a metal from the metal layer into the oxide layer.Type: ApplicationFiled: December 14, 2015Publication date: June 15, 2017Inventors: Michael P. Chudzik, Min Dai, Dominic J. Schepis, Shahab Siddiqui
-
Patent number: 9679810Abstract: An aspect of the disclosure is directed to a method of forming an interconnect for use in an integrated circuit. The method comprises: forming an opening in a dielectric layer on a substrate; filling the opening with a metal such that an overburden outside of the opening is created; subjecting the metal to a microwave energy dose such that atoms from the overburden migrate to within the opening; and planarizing the metal to a top surface of the opening to remove the overburden, thereby forming the interconnect.Type: GrantFiled: February 11, 2016Date of Patent: June 13, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Joyeeta Nag, Shishir K. Ray, Andrew H. Simon, Oleg Gluschenkov, Siddarth A. Krishnan, Michael P. Chudzik
-
Patent number: 9673108Abstract: A method of manufacturing a semiconductor structure, and the resultant structure. The method includes forming an oxide layer above a substrate. The method includes forming a metal layer above the oxide layer. The method includes forming a first capping layer above the metal layer. A material forming the first capping layer may be titanium oxide, or titanium oxynitride. The method includes annealing the semiconductor structure. Annealing the semiconductor structure may result in diffusing a metal from the metal layer into the oxide layer.Type: GrantFiled: December 14, 2015Date of Patent: June 6, 2017Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, Min Dai, Dominic J. Schepis, Shahab Siddiqui
-
Patent number: 9653534Abstract: A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.Type: GrantFiled: December 17, 2014Date of Patent: May 16, 2017Assignee: International Business Machines CorporationInventors: Takashi Ando, Eduard A. Cartier, Michael P. Chudzik, Aritra Dasgupta, Herbert L. Ho, Donghun Kang, Rishikesh Krishnan, Vijay Narayanan, Kern Rim
-
Patent number: 9627508Abstract: A semiconductor structure includes a substrate and an intrinsic replacement channel. A tunneling field effect transistor (TFET) fin may be formed by the intrinsic replacement channel, a p-fin and an n-fin formed upon the substrate. The p-fin may serve as the source of the TFET and the n-fin may serve as the drain of the TFET. The replacement channel may be formed in place of a sacrificial channel of a diode fin that includes the p-fin, the n-fin, and the sacrificial channel at the p-fin and n-fin junction.Type: GrantFiled: April 14, 2015Date of Patent: April 18, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Michael P. Chudzik, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan, Jeffrey W. Sleight
-
Patent number: 9577100Abstract: A semiconductor device including at least one suspended channel structure of a silicon including material, and a gate structure present on the suspended channel structure. At least one gate dielectric layer is present surrounding the suspended channel structure, and at least one gate conductor is present on the at least one gate dielectric layer. Source and drain structures may be composed of a silicon and germanium including material. The source and drain structures are in contact with the source and drain region ends of the suspended channel structure through a silicon cladding layer.Type: GrantFiled: June 16, 2014Date of Patent: February 21, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Kangguo Cheng, Michael P. Chudzik, Eric C. Harley, Judson R. Holt, Yue Ke, Rishikesh Krishnan, Kern Rim, Henry K. Utomo
-
Patent number: 9564505Abstract: Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.Type: GrantFiled: April 17, 2014Date of Patent: February 7, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Michael P. Chudzik, Martin M. Frank, Herbert L. Ho, Mark J. Hurley, Rashmi Jha, Naim Moumen, Vijay Narayanan, Dae-Gyu Park, Vamsi K. Paruchuri
-
Patent number: 9536985Abstract: A method for producing a semiconductor structure, as well as a semiconductor structure, that uses a partial removal of an insulating layer around a semiconductor fin, and subsequently epitaxially growing an additional semiconductor material in the exposed regions, while maintaining the shape of the fin with the insulating layer.Type: GrantFiled: September 29, 2014Date of Patent: January 3, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Michael P. Chudzik, Brian J. Greene, Eric C. T. Harley, Judson R. Holt, Yue Ke, Rishikesh Krishnan, Renee T. Mo, Yinxiao Yang
-
Patent number: 9524986Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a high-mobility fin field effect transistor (finFET) fin in a silicon semiconductor on insulator (SOI) substrate by trapping crystalline lattice dislocations that occur during epitaxial growth in a recess formed in a semiconductor layer. The crystalline lattice dislocations may remain trapped below a thin isolation layer, thereby reducing device thickness and the need for high-aspect ratio etching and fin formation.Type: GrantFiled: June 26, 2014Date of Patent: December 20, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Michael P. Chudzik, Ramachandra Divakaruni, Judson R. Holt, Arvind Kumar, Unoh Kwon
-
Patent number: 9478425Abstract: A method of manufacturing a semiconductor structure, and the resultant structure. The method includes forming an oxide layer above a substrate. The method includes forming a metal layer above the oxide layer. The method includes forming a first capping layer above the metal layer. A material forming the first capping layer may be titanium oxide, or titanium oxynitride. The method includes annealing the semiconductor structure. Annealing the semiconductor structure may result in diffusing a metal from the metal layer into the oxide layer.Type: GrantFiled: February 17, 2016Date of Patent: October 25, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, Min Dai, Dominic J. Schepis, Shahab Siddiqui
-
Publication number: 20160308025Abstract: A semiconductor structure includes a substrate and an intrinsic replacement channel. A tunneling field effect transistor (TFET) fin may be formed by the intrinsic replacement channel, a p-fin and an n-fin formed upon the substrate. The p-fin may serve as the source of the TFET and the n-fin may serve as the drain of the TFET. The replacement channel may be formed in place of a sacrificial channel of a diode fin that includes the p-fin, the n-fin, and the sacrificial channel at the p-fin and n-fin junction.Type: ApplicationFiled: April 14, 2015Publication date: October 20, 2016Inventors: Michael P. Chudzik, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan, Jeffrey W. Sleight
-
Patent number: 9437496Abstract: A semiconductor device such as a FinFET includes a plurality of fins formed upon a substrate and a gate covering a portion of the fins. Diamond-shaped volumes are formed on the sidewalls of the fins by epitaxial growth which may be limited to avoid merging of the volumes or where the epitaxy volumes have merged. Because of the difficulties in managing merging of the diamond-shaped volumes, a controlled merger of the diamond-shaped volumes includes depositing an amorphous semiconductor material upon the diamond-shaped volumes and a crystallization process to crystallize the deposited semiconductor material on the diamond-shaped volumes to fabricate controllable and uniformly merged source drain.Type: GrantFiled: June 1, 2015Date of Patent: September 6, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Michael P. Chudzik, Brian J. Greene, Edward P. Maciejewski, Kevin McStay, Shreesh Narasimha, Chengwen Pei, Werner A. Rausch
-
Patent number: 9431289Abstract: Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen contamination while avoiding alteration of work function and switching threshold shift in transistors including such Hi-K materials.Type: GrantFiled: June 17, 2015Date of Patent: August 30, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Christopher V. Baiocco, Michael P. Chudzik, Deleep R. Nair, Jay M. Shah
-
Patent number: 9397177Abstract: A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks.Type: GrantFiled: November 25, 2013Date of Patent: July 19, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Michael P. Chudzik, Siddarth A. Krishnan, Unoh Kwon