Abstract: A first thread is executed in a first pipeline of a first core of an integrated circuit (IC). The first core includes a first set of hardware structures. A second thread is executed in a second pipeline of a second core of the IC. The second core includes a second set of hardware structures. In response to a command to operate the IC with a unified core, the first core is combined with the second core to obtain the unified core. To unify the first core, the first pipeline is unified with the second pipeline to obtain a unified pipeline, and the first set of hardware structures is unified with the second set of hardware structures to obtain a unified set of hardware structures. A single thread is executed in the unified pipeline of the unified core using the unified set of hardware structures.

Abstract: A first thread is executed in a first pipeline of a first core of an integrated circuit (IC). The first core includes a first set of hardware structures. A second thread is executed in a second pipeline of a second core of the IC. The second core includes a second set of hardware structures. In response to a command to operate the IC with a unified core, the first core is combined with the second core to obtain the unified core. To unify the first core, the first pipeline is unified with the second pipeline to obtain a unified pipeline, and the first set of hardware structures is unified with the second set of hardware structures to obtain a unified set of hardware structures. A single thread is executed in the unified pipeline of the unified core using the unified set of hardware structures.

Abstract: A first thread is executed in a first pipeline of a first core of an integrated circuit (IC). The first core includes a first set of hardware structures. Response to a command to operate the IC with multiple cores, the first pipeline is flushed. The first core is partitioned to obtain a second core and a third core. The first pipeline is partitioned to obtain a second pipeline and a third pipeline. The first set of hardware structures is partitioned to obtain a second set of hardware structures and a third set of hardware structures. The first thread is executed on the second pipeline of the second core of the IC, the second core including the second set of hardware structures. A second thread is executed on the third pipeline of the third core of the IC, the third core including the third set of hardware structures.

Abstract: A communication system is described providing for access to registers over a control register access bus. The system includes one or more core units including one or more addressable core registers, wherein the units are coupled to the communication bus. The system also includes one or more core clusters (CCLUSTERs) coupled to the one or more core units through the communication bus. The CCLUSTERs provide one or more gateways for transactions to and from the one or more core units. The system also includes a request ordering and coherency (ROC) unit coupled to the CCLUSTERs through the communication bus that is configured for scheduling transactions relating to the registers onto the communication bus. The system also includes the one or more addressable registers that are located in the ROC unit, the CCLUSTERs, and the one or more core units.

Abstract: A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events.

Abstract: A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events.

Abstract: A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events.

Abstract: A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events.

Abstract: A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events.

Abstract: A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events.

Abstract: A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events.

Abstract: In one embodiment, a method for flow optimization and prediction for vector streaming single instruction, multiple data (SIMD) extension (VSSE) memory operations is disclosed. The method comprises generating an optimized micro-operation (?op) flow for an instruction to operate on a vector if the instruction is predicted to be unmasked and unit-stride, the instruction to access elements in memory, and accessing via the optimized ?op flow two or more of the elements at the same time without determining masks of the two or more elements. Other embodiments are also described.

Abstract: Methods and apparatus, including computer program products, for a microinstruction pointer stack in a processor. A method executed in a processor includes executing microcode (?code) addressed by pointers stored in an out-of-order microinstruction pointer (?IP) stack, and manipulating the ?IP stack with a set of microinstructions.

Abstract: A microprocessor uses broadcast state renaming to reduce processing delays and microcode overhead which would otherwise result from rebroadcasts of state due to register renaming. The microprocessor comprises a memory execution unit, a microcode sequencer, and various functional units. The memory execution unit includes a segment register, content of which represents state of the processor. The microcode sequencer sets an identifier field in at least some microinstructions, indicating which of multiple copies of broadcast state are to be used in processing each such microinstruction. Each functional unit receives and internally stores multiple copies of broadcast state, each of which may correspond to a different renamed version of the segment register. Each functional unit selects, based on the identifier field of a microinstruction, one of its internally stored copies of broadcast state for use in processing the microinstruction.

Abstract: A method executed in a processor includes executing microcode (&mgr;code) stored in an out-of-order microinstruction pointer (&mgr;IP) stack and manipulating the &mgr;IP stack with a set of microinstructions.

Abstract: A microprocessor uses broadcast state renaming to reduce processing delays and microcode overhead which would otherwise result from rebroadcasts of state due to register renaming. The microprocessor comprises a memory execution unit, a microcode sequencer, and various functional units. The memory execution unit includes a segment register, content of which represents state of the processor. The microcode sequencer sets an identifier field in at least some microinstructions, indicating which of multiple copies of broadcast state are to be used in processing each such microinstruction. Each functional unit receives and internally stores multiple copies of broadcast state, each of which may correspond to a different renamed version of the segment register. Each functional unit selects, based on the identifier field of a microinstruction, one of its internally stored copies of broadcast state for use in processing the microinstruction.