Abstract: A pipelined data processor has instructions at different stages of execution. Some of the instructions specify virtual addresses into a file of registers having physical addresses. A speculative translator maps the virtual registers of an instruction at one pipeline stage into physical registers for speculative use by the instruction at a later pipeline stage. The registers have multiple differently translated regions. Failure of speculative renaming reverts to an archive copy of renaming data.

Abstract: An apparatus is provided for detecting instruction ordering dependencies. The apparatus includes a plurality of address comparators. Each comparator including a first input adapted to receive a first operand address from one of a plurality of instructions; a second input adapted to receive a second operand address from a second one of a plurality of instructions; and an output to transmit a logic signal responsive to a match between the first and second operand addresses. The address comparators receive the first operand address from a respective, different ones of the plurality of instructions; and a hardware structure to receive the match indications from the address comparators and to indicate a dependency responsive to the match indications from a first one and a second one of the address comparators. A method is provided for detecting instruction dependencies.

Abstract: A loop branch prediction system is provided to predict a final iteration of a loop and resteer an associated fetch module to an appropriate target address. The loop prediction system includes a counter and an end of loop (EOL) module. In one mode, the counter tracks loop branches in process. When a termination condition is detected, the counter switches to a second mode to track the number of loop branches still to be issued. The EOL module compares the number of loop branches still to be issued with one or more threshold values and generates a resteer signal when a match is detected.

Abstract: A dispersal unit in combination with a chain affinity unit and an intra-cycle dependency analyzer routes instructions in a microprocessor in order to improve microprocessor performance. The dispersal unit routes instructions to a particular cluster in the microprocessor in response to information stored in the chain affinity unit. The intra-cycle dependency analyzer identifies dependencies in groups of instructions to the dispersal unit, and the dispersal unit routes instructions in the group based on those dependencies.

Abstract: A dispersal unit in combination with a chain affinity unit and an intra-cycle dependency analyzer routes instructions in a microprocessor in order to improve microprocessor performance. The dispersal unit routes instructions to a particular cluster in the microprocessor in response to information stored in the chain affinity unit. The intra-cycle dependency analyzer identifies dependencies in groups of instructions to the dispersal unit, and the dispersal unit routes instructions in the group based on those dependencies.

Abstract: A processor architecture with an instruction set having a predict instruction, the predict instruction providing static prediction information and a statically predicted target address to the processor for a branch instruction. The processor decodes a predict instruction to obtain an associated pair of addresses comprising a predicted target address and a referenced instruction address, and fetches a predicted target instruction having an instruction address matching the predicted target address when a fetched and decoded branch instruction has an instruction address matching the referenced instruction address.