Abstract: In automatic test equipment the logical levels on certain of the test pins are set to 0 and 1 by corresponding flip-flops included in respective I/O logic circuits. The states of the flip-flops (as well as other factors) are controlled by commands read out of a control RAM which is of sufficient width to provide a 4-bit command on lines for each logic circuit. The available commands include NOP commands and change commands which toggle the states of the corresponding flip-flops. A relatively small number of addresses of the control RAM have change commands entered in correspondence with selected ones of the pins. By repeatedly reading out the commands in these addresses in a non-cyclic sequence it is possible to generate a succession of different states of the flip-flops in the logic, which succession is much longer than the number of addresses of the control RAM which are utilized. Apparatus for establishing the correct addressing sequence is described.