Patents by Inventor Michael P. Daly

Michael P. Daly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10263337
    Abstract: An aspect of the present invention is drawn to a communication system that includes an electrically steerable parasitic array transmitter antenna, a transmitter driver, an electrically steerable parasitic array receiver antenna, and a receiver driver. The transmitter driver is arranged such that it is operable to enable the electrically steerable parasitic array transmitter antenna to transmit a beam having a first directional vector at a first time, a second directional vector at a second time, and an nth directional vector at an nth time. The receiver driver is arranged such that it is operable to enable the electrically steerable parasitic array receiver antenna to receive a beam having a third directional vector at a third time, a fourth directional vector at a fourth time, and an mth directional vector at an mth time.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: April 16, 2019
    Assignee: The United States of America as represented by Secretary of the Navy
    Inventor: Michael P. Daly
  • Patent number: 10141647
    Abstract: An antenna comprising: a ground plane having a center; six receive ports mounted to the ground plane in a circular configuration around the center and separated from each other by approximately 60 degrees; three conductive half-loops, disposed in mutually orthogonal planes, wherein each half-loop has two ends that are connected to separate receive ports; and three 180° hybrids, each 180° hybrid having two input ports, a delta output port, and a sum output port, wherein the two input ports of each 180° hybrid are connected to the two receive ports of one of the half-loops.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: November 27, 2018
    Assignee: The United States of America as represented by Secretary of the Navy
    Inventors: John W. Rockway, John H. Meloling, Michael P. Daly
  • Patent number: 10141648
    Abstract: An antenna comprising: a loop made of conductive material; two baluns connected to, and intersecting, opposing sides of the loop, wherein each balun has an output; a 180° hybrid coupler having two input ports, a sum output port, and a delta output port, wherein the two input ports are connected to the outputs of the baluns; a first low noise amplifier (LNA) connected to the sum output port; a second LNA connected to the delta output port; first and second receivers connected to the first and second LNAs respectively; and wherein the antenna is electrically small and is designed to simultaneously receive wideband signals in real time from 3 to 30 MHz.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: November 27, 2018
    Assignee: The United States of America, as Represented by the Secretary of the Navy
    Inventors: John W. Rockway, John H. Meloling, Aldo Monges, Michael P. Daly
  • Publication number: 20180265231
    Abstract: A cyclic packaging process, such as VFFS or HFFS, packages a product with a viscosity of ?100,000 centipoise without leaving substantial air pockets in the package, by utilizing a means (38) for restricting upstream flow of viscous product in the strand of tubing (24). The result is that packages of uniform weight of the viscous product can be made without substantial air pockets therein, and without having to use metal clips. An apparatus (10) for carrying out the process is disclosed.
    Type: Application
    Filed: September 21, 2016
    Publication date: September 20, 2018
    Inventors: Timothy Gray Caudle, Matthew F. Ellis, Csaba F. Kiss, Joseph E. Moon, Dwight H. Smith, Michael P. Daly
  • Publication number: 20180076523
    Abstract: An antenna comprising: a loop made of conductive material; two baluns connected to, and intersecting, opposing sides of the loop, wherein each balun has an output; a 180° hybrid coupler having two input ports, a sum output port, and a delta output port, wherein the two input ports are connected to the outputs of the baluns; a first low noise amplifier (LNA) connected to the sum output port; a second LNA connected to the delta output port; first and second receivers connected to the first and second LNAs respectively; and wherein the antenna is electrically small and is designed to simultaneously receive wideband signals in real time from 3 to 30 MHz.
    Type: Application
    Filed: September 21, 2016
    Publication date: March 15, 2018
    Inventors: John W. Rockway, John H. Meloling, Aldo Monges, Michael P. Daly
  • Publication number: 20180076522
    Abstract: An antenna comprising: a ground plane having a center; six receive ports mounted to the ground plane in a circular configuration around the center and separated from each other by approximately 60 degrees; three conductive half-loops, disposed in mutually orthogonal planes, wherein each half-loop has two ends that are connected to separate receive ports; and three 180° hybrids, each 180° hybrid having two input ports, a delta output port, and a sum output port, wherein the two input ports of each 180° hybrid are connected to the two receive ports of one of the half-loops.
    Type: Application
    Filed: September 13, 2016
    Publication date: March 15, 2018
    Inventors: John W. Rockway, John H. Meloling, Michael P. Daly
  • Patent number: 8581440
    Abstract: An adaptive phase offset controller for use with a switching power converter having first and second channels. The controller includes a discriminator which detects a ‘critical condition’ in which a switching signal for the first channel transitions during a critical time interval so as to give rise to crosstalk that can corrupt the operation of the second channel's control circuit. When the discriminator detects a critical condition, a phase offset circuit offsets the phase of the first channel's switching signals, such that subsequent transitions occur outside of the critical time interval. A second discriminator and phase offset circuit are preferably employed to detect critical conditions which can give rise to crosstalk that can corrupt the operation of the first channel's control circuit.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: November 12, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Lawrence H. Edelson, Michael P. Daly, Trey Roessig
  • Patent number: 8035538
    Abstract: A sigma-delta converter suitable for measuring a photocurrent comprises an input node adapted to receive a current to be measured (Imeas), a capacitor connected to the input node, a clocked comparator coupled to the input node and to a reference voltage Vref at respective inputs, and a switchable current source connected to the input node which conducts a reference current Iref when switched on. The converter is arranged in a sigma-delta configuration, with the current source switched on to pull down the voltage (VCMP) at the input node when the comparator output toggles due to VCMP increasing above Vref, and to be switched off when the comparator output toggles due to VCMP falling below Vref, such that the comparator output comprises a digital bitstream which varies with Imeas.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: October 11, 2011
    Assignee: Analog Devices, Inc.
    Inventors: Lawrence H. Edelson, Michael P. Daly, Trey A. Roessig
  • Publication number: 20110049986
    Abstract: An adaptive phase offset controller for use with a switching power converter having first and second channels. The controller includes a discriminator which detects a ‘critical condition’ in which a switching signal for the first channel transitions during a critical time interval so as to give rise to crosstalk that can corrupt the operation of the second channel's control circuit. When the discriminator detects a critical condition, a phase offset circuit offsets the phase of the first channel's switching signals, such that subsequent transitions occur outside of the critical time interval. A second discriminator and phase offset circuit are preferably employed to detect critical conditions which can give rise to crosstalk that can corrupt the operation of the first channel's control circuit.
    Type: Application
    Filed: August 25, 2010
    Publication date: March 3, 2011
    Inventors: Lawrence H. EDELSON, Michael P. Daly, Trey Roessig
  • Publication number: 20100097257
    Abstract: A sigma-delta converter suitable for measuring a photocurrent comprises an input node adapted to receive a current to be measured (Imeas), a capacitor connected to the input node, a clocked comparator coupled to the input node and to a reference voltage Vref at respective inputs, and a switchable current source connected to the input node which conducts a reference current Iref when switched on. The converter is arranged in a sigma-delta configuration, with the current source switched on to pull down the voltage (VCMP) at the input node when the comparator output toggles due to VCMP increasing above Vref, and to be switched off when the comparator output toggles due to VCMP falling below Vref, such that the comparator output comprises a digital bitstream which varies with Imeas .
    Type: Application
    Filed: December 16, 2009
    Publication date: April 22, 2010
    Inventors: Lawrence H. EDELSON, Michael P. DALY, Trey A. ROESSIG
  • Patent number: 7659840
    Abstract: A sigma-delta converter suitable for measuring a photocurrent comprises an input node adapted to receive a current to be measured (Imeas), a capacitor connected to the input node, a clocked comparator coupled to the input node and to a reference voltage Vref at respective inputs, and a switchable current source connected to the input node which conducts a reference current Iref when switched on. The converter is arranged in a sigma-delta configuration, with the current source switched on to pull down the voltage (VCMP) at the input node when the comparator output toggles due to VCMP increasing above Vref, and to be switched off when the comparator output toggles due to VCMP falling below Vref, such that the comparator output comprises a digital bitstream which varies with Imeas.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: February 9, 2010
    Assignee: Analog Devices, Inc.
    Inventors: Lawrence H. Edelson, Michael P. Daly, Trey A. Roessig
  • Publication number: 20090207061
    Abstract: A sigma-delta converter suitable for measuring a photocurrent comprises an input node adapted to receive a current to be measured (Imeas), a capacitor connected to the input node, a clocked comparator coupled to the input node and to a reference voltage Vref at respective inputs, and a switchable current source connected to the input node which conducts a reference current Iref when switched on. The converter is arranged in a sigma-delta configuration, with the current source switched on to pull down the voltage (VCMP) at the input node when the comparator output toggles due to VCMP increasing above Vref, and to be switched off when the comparator output toggles due to VCMP falling below Vref, such that the comparator output comprises a digital bitstream which varies with Imeas.
    Type: Application
    Filed: February 15, 2008
    Publication date: August 20, 2009
    Inventors: Lawrence H. Edelson, Michael P. Daly, Trey A. Roessig
  • Patent number: 7266077
    Abstract: A serial digital communication system includes a master device and a plurality of slave devices connected serially between the master device's output and input—thereby forming a closed chain. Each slave device transmits a predetermined number of PWM pulses to the device following it in the chain upon receipt of an end-of-transmission (EOT) signal from the device preceding it in the chain, and transmits an EOT signal when the transmission of its PWM pulses is completed. The master device transmits an EOT signal to initiate the transmission of PWM pulses from each slave device. Each slave device passively buffers PWM pulses received from the preceding device, such that PWM pulses are transmitted in one direction sequentially to the input of the master device via the intervening slave device.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: September 4, 2007
    Assignee: Analog Devices, Inc.
    Inventors: Michael P. Daly, David Thomson
  • Patent number: 7228373
    Abstract: A communication system includes a master device which communicates with a chain of serially-connected slave devices. The master originates messages, each of which is intended for a particular ‘target’ slave device. Each message contains a ‘distance to target device’ value equal to the number of devices between the master and target, and a data packet containing data to be conveyed between the master and target. Each slave device determines if the ‘distance to target device’ value indicates that it is the target. If not, the slave device increments or decrements the value in real time, with no latency, and transmits the modified message to the next slave device until received by the target device. In one embodiment, the target device may place data in the data packet, and the slave devices are arranged to buffer the data back to the master device.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: June 5, 2007
    Assignee: Analog Devices, Inc.
    Inventors: Michael P. Daly, Jonathan M. Audy
  • Patent number: 7112948
    Abstract: A voltage source includes first and second pn junctions which conduct the outputs of respective current sources to establish respective base-emitter voltages Vbe1 and Vbe2 at respective nodes; Vbe1 and Vbe2 can each be generated with a current I or a current N*I. An amplifier A1 has its non-inverting input connected to the second node and its inverting input connected to the first node through an input capacitor; a feedback capacitor is connected between the inverting input and a third node. Switches are connected between A1's inverting input and A1's output, between the third node and A1's output, and between the third node and a circuit common point. A control circuit operates the switches and current sources during first and second operating phases to selectively produce a temperature independent output voltage or a temperature dependent output voltage.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: September 26, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Michael P. Daly, Evaldo M. Miranda, David Thomson, A. Paul Brokaw
  • Publication number: 20030020552
    Abstract: An extended range of frequency synthesiser responsive to a number of different input frequencies to provide multiples of those input frequencies as its final outputs includes a phase locked loop having an output frequency range containing a multiple of each of the final output frequencies; and a pre-divider circuit for dividing the input frequencies by a first predetermined number before submission to said phase locked loop and a post divider circuit for dividing the phase locked loop output by a second predetermined number to obtain the final output while operating the phase locked loop in the output frequency range.
    Type: Application
    Filed: May 28, 2002
    Publication date: January 30, 2003
    Inventors: Vincent J. Troy, Michael P. Daly, Brian S. Carroll, Martin Gerard Cotter
  • Patent number: 6236087
    Abstract: An input protection device is provided for protecting a circuit structure which is coupled to a first node, the device comprising a first lightly-doped region of P-type material with a lightly doped well of N-type material formed in it. Two regions of heavily doped N-type and P-type material, which are electrically connected to the first node, are formed in the well of N-type material. A third heavily doped region of N type material is formed in the first lightly-doped region of P-type material and is electrically connected to a reference node. In a first aspect of this invention, the third heavily doped region of N type material is formed in a second well of N-type material, which in turn is formed in the first lightly-doped region of P-type material. In this first aspect of the invention a further region of heavily doped P-type material is formed in the second well of N-type material, this further region of heavily doped P-type material being electrically connected to the reference node.
    Type: Grant
    Filed: November 2, 1998
    Date of Patent: May 22, 2001
    Assignee: Analog Devices, Inc.
    Inventors: Michael P. Daly, Denis Ellis, Keith A. Moloney, Liam J. White, Brian A. Moane, Kieran Heffernan, Denis Joseph Doyle, Michael G. Tuthill, David John Clarke