Abstract: High density fiber interfaces for silicon photonics based integrated-optics products are provided via a system or device that includes: a prism configured to reflect, via a lensed reflecting surface, a plurality of optical signals between a first surface and a second surface at a non-normal angle of incidence; a photonic interposer including a plurality of grating couplers corresponding to the plurality of optical signals that are arranged in a two-dimensional array and that are optically connected directly to the first surface of the prism; and a plurality of optical fibers that are arranged in the two-dimensional array and that are optically connected directly to the second surface of the prism.

Abstract: This disclosure is directed to a wireless device with a suppressor that couples to the aggressor signal of a frequency source to generate a cancelling signal for suppressing spurs resulting from operation of the frequency source. The amplitude and phase delay of the cancelling signal are adjusted to optimize the cancellation of the spur. Preferably, a calibration routine is performed to establish appropriate delay and amplitude values to cancel the spurs occurring at each device gain setting.

Abstract: A device and method for adjusting transmit power in a wireless communication device. The wireless communication device comprises a transmitter having a power amplifier, wherein the amplifier may introduce distortion into the transmit signal. The method may periodically determine an error vector magnitude (EVM) level in the transmitter of the wireless communication device. The EVM level may be determined based on differences between an ideal transmit signal without amplification, and an actual transmit signal with amplification. The method may then adjust one or more transmit gain settings of at least one gain stage of the wireless device based on the measured EVM level in the transmitter. In one embodiment, as the EVM increases, indicating that more distortion is being introduced, the method may reduce the gain settings of the gain stage(s) to reduce this distortion. If the EVM decreases, the method may increase the gain of the gain stage(s).

Abstract: This disclosure is directed to a wireless device with a suppressor that couples to the aggressor signal of a frequency source to generate a cancelling signal for suppressing spurs resulting from operation of the frequency source. The amplitude and phase delay of the cancelling signal are adjusted to optimize the cancellation of the spur. Preferably, a calibration routine is performed to establish appropriate delay and amplitude values to cancel the spurs occurring at each device gain setting.

Abstract: A method and apparatus for configuring an oscillator circuit to selectively switch between a low power mode and a normal mode of operation. The oscillator circuit includes an oscillator core in parallel with a dynamically configurable gain circuit. The oscillator core is configured to generate a clock signal. One or more gain elements of the gain circuit can be selectively disabled to reduce the operating power level of the oscillator circuit during a low power mode.

Abstract: A method and apparatus for configuring an oscillator circuit to selectively switch between a low power mode and a normal mode of operation. The oscillator circuit includes an oscillator core in parallel with a dynamically configurable gain circuit. The oscillator core is configured to generate a clock signal. One or more gain elements of the gain circuit can be selectively disabled to reduce the operating power level of the oscillator circuit during a low power mode.

Abstract: A method and apparatus for protecting an input-out (I/O) circuit against electro-static discharge (ESD) events. An ESD circuit used to protect the I/O circuit against an ESD event is coupled to the I/O circuit. The ESD circuit includes a diode clamp circuit that couples an I/O pad to a power supply and a ground pad. The ESD circuit further includes an active clamp circuit that is configured to clamp the I/O pad without turning on the diode clamp circuit during the ESD event.

Abstract: A system and/or integrated circuit are disclosed that may include a receiver, a harmonic signal generator and a signal injector. The receiver may use at least one signal line to create a baseband signal to further create a quality measure used to improve the quality of reception and based upon the receiver response to the baseband signal. The harmonic signal generator may generate harmonic signal(s) including at least one harmonic component within the receiver's reception range. The signal injector may receive the harmonic signal and a control signal to generate the signal line from the harmonic signal in response to the control signal. The receiver may implement WLAN, Bluetooth, GPS, AM, mobile TV, FM, and/or Television. A transmitter compatible with the receiver may or may not be included, and may be configured to couple at least one of its outputs to the receiver to create a second quality measure.

Abstract: A method of generating a quadrature local oscillator (LO) frequencies is provided. In this method, a voltage-controlled oscillator (VCO) frequency can be mixed with a divided version of the VCO frequency to generate mixed signals. A lower sideband of the mixed signals can be selected for the quadrature LO frequencies to minimize the occurrence of spurs. Notably, the divided version is 1/N of the VCO frequency and the VCO frequency is a radio frequency (RF) channel frequency times a ratio N/(N?1).

Abstract: A method of generating a quadrature local oscillator (LO) frequencies is provided. In this method, a voltage-controlled oscillator (VCO) frequency can be mixed with a divided version of the VCO frequency to generate mixed signals. A lower sideband of the mixed signals can be selected for the quadrature LO frequencies to minimize the occurrence of spurs. Notably, the divided version is 1/N of the VCO frequency and the VCO frequency is a radio frequency (RF) channel frequency times a ratio N/(N?1).

Abstract: A method of providing current mode pulse frequency modulation (PFM) for a switching regulator can include resetting a driver input for a fixed duration when a first current in the driver reaches a first value set by an error amplifier output. The first current can be associated with PMOS switching transistors in the driver. The method can also include setting the driver input signal for the same fixed duration when a second current in the driver reaches a second value. This second current can be associated with NMOS switching transistors in the driver. In one embodiment, the driver can be tristated to ignore both the resetting and the setting. Using this method, perturbations of the inductor current can be substantially corrected and have limited impact on the current waveform beyond the cycle in which they occur.

Abstract: Using separate synthesizers in a radio frequency (RF) device can facilitate avoiding interference. Specifically, a first synthesizer can be programmed to generate a first output frequency signal having an Frf frequency. A second synthesizer can be programmed to generate a second output frequency signal having an Fif frequency. Notably, a sum of the Frf and Fif frequencies equals an Fchannel frequency of the RF device. Thus, any RF channel can be received (or transmitted) with a plurality of VCO frequencies for each of the two synthesizers. A table of Frf/Fif combinations can be used to determine an Frf/Fif combination that avoids a known interfering source. Alternatively, Frf/Fif combinations can be randomly chosen until an interfering source is avoided.

Abstract: A frequency synthesizer and a method for frequency synthesis are disclosed. The frequency synthesizer comprises a voltage controlled oscillator for generating an output signal having a synthesized frequency, and a prescaler connected to the VCO for receiving the output signal and providing a feedback signal. The prescaler programmatically selects between an integer divider value and a fractional divider value to divide the synthesized frequency of the output signal.

Abstract: A frequency synthesizer and a method for frequency synthesis are disclosed. The frequency synthesizer comprises a voltage controlled oscillator for generating an output signal having a synthesized frequency, and a prescaler connected to the VCO for receiving the output signal and providing a feedback signal. The prescaler programmatically selects between an integer divider value and a fractional divider value to divide the synthesized frequency of the output signal.

Abstract: A pulse width distortion correction logic level converter converts differential logic while preserving the pulse width of the original signal. The converter converts a differential input signal to a single-ended signal having a same pulse width as the differential input signal. The present invention receives and converts the differential input signal at a first converter and a second converter, wherein the first converter generates a first output signal, and the second converter generates a second output signal, respectively. Latching the first output signal of the first converter and the second output signal of the second converter produces a fill swing single-ended output signal having the same pulse width as the input differential signal. The first output signal sets the latching device with an edge of the first output signal of the first converter and resets the latching device with an edge of the second output signal of the second converter.

Abstract: A pulse width distortion correction logic level converter that converts differential logic while preserving the pulse width of the original signal. The converter converts a differential input signal to a single-ended signal having a same pulse width as the differential input signal. The present invention receives and converts the differential input signal at a first and a second converter, wherein the first converter generates a first output signal and the second converter generates a second output signal, respectively. Latching the first output signal of the first converter and the second output signal of the second converter produces a fill swing single-ended output signal having the same pulse width as the input differential signal. The first output signal sets the latching device with an edge of the first output signal of the first converter and resets the latching device with an edge of the second output signal of the second converter.

Abstract: A pulse width distortion correction logic level converter converts differential logic while preserving the pulse width of the original signal. The converter converts a differential input signal to a single-ended signal having a same pulse width as the differential input signal. The present invention receives and converts the differential input signal at a first converter and a second converter, wherein the first converter generates a first output signal, and the second converter generates a second output signal, respectively. Latching the first output signal of the first converter and the second output signal of the second converter produces a full swing single-ended output signal having the same pulse width as the input differential signal. The first output signal sets the latching device with an edge of the first output signal of the first converter and resets the latching device with an edge of the second output signal of the second converter.

Abstract: An adaptive equalizer is configured to reconstruct electronic signals which are transmitted over signal cables, such as twisted pair cables. The equalizer satisfactorily reconstructs the signals over a broad range of cable lengths. Using the known degradation characteristics for a cable over a desired range of lengths, the adaptive equalizer includes multiple equalization paths, each of which are configured to reconstruct the input voltage signal optimized for a particular cable length. The degraded input signal is split according to a predetermined relationship into an appropriate two of the multiple equalization paths as controlled by a control logic circuit. Though each path is optimized to reconstruct the signal for a particular length of cable, the adaptive control adds a function of the actual cable length for more accurately reconstructing the signal. Each of the two active paths forms a partially reconstructed signal which is summed to form a composite reconstructed output signal.

Abstract: A transmission termination circuit able to reduce transmission signal reflections and resultant data corruption such that a single network may selectively communicate data using either a voltage driven transceiver or a current driven transceiver. A 10BASE-T transceiver has differential voltage driven outputs. A first output is coupled to a first terminal of a primary winding of a transformer through a first resistor. A second output is coupled to a second terminal of the first primary winding through a second resistor. A 100BASE-TX transceiver has differential current driven outputs. A first output is coupled to a first terminal of a second primary winding of the transformer. A second output is coupled to a second terminal of the second primary winding. A resistive snubber comprising a resistor in series with a capacitor is coupled across the 100BASE-TX outputs. A twisted-pair network is coupled to a secondary winding of the transformer.