Patents by Inventor Michael P. Skinner
Michael P. Skinner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9818672Abstract: Embodiments of flow diversion devices (FDDs) are disclosed herein. An FDD may include a body formed of a body material and a plurality of thermally deformable fins arranged along the body. Individual fins of the plurality of fins may include first and second materials having different coefficients of thermal expansion (CTEs). Other embodiments may be disclosed and/or claimed.Type: GrantFiled: February 14, 2014Date of Patent: November 14, 2017Assignee: INTEL IP CORPORATIONInventors: Michael P. Skinner, Sven Albers, Harald Gossner, Peter Baumgartner, Hans-Joachim Barth
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Patent number: 9778688Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package. In embodiments, an integrated circuit (IC) package may include a flexible substrate. The flexible substrate may have a plurality of dies coupled therewith. The IC package may include a first encapsulation material, having a first rigidity, disposed on the flexible substrate to at least partially encapsulate each die of the plurality dies. The IC package may further include a second encapsulation material, having a second rigidity, disposed on the flexible substrate. In embodiments, the second rigidity and the first rigidity are different from one another. Other embodiments may be described and/or claimed.Type: GrantFiled: November 12, 2014Date of Patent: October 3, 2017Assignee: INTEL CORPORATIONInventors: Jiamiao Tang, Junfeng Zhao, Michael P. Skinner, Yong She, Jiun Hann Sir, Bok Eng Cheah, Shanggar Periaman, Kooi Chi Ooi, Yen Hsiang Chew
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Integrated circuit packaging techniques and configurations for small form-factor or wearable devices
Patent number: 9646953Abstract: Embodiments of the present disclosure are directed toward integrated circuit (IC) packaging techniques and configurations for small form-factor or wearable devices. In one embodiment, an apparatus may include a substrate having a first side and a second side disposed opposite to the first side and a sidewall disposed between the first side and the second side, the sidewall defining a perimeter of the substrate, and a plurality of through-substrate vias (TSVs) disposed between the first side and the second side of the substrate, and a first dielectric layer disposed on the first side and including electrical routing features to route electrical signals of one or more dies in a plane of the first dielectric layer. Other embodiments may be described and/or claimed.Type: GrantFiled: November 12, 2014Date of Patent: May 9, 2017Assignee: INTEL CORPORATIONInventors: Jackson Chung Peng Kong, Bok Eng Cheah, Kooi Chi Ooi, Shanggar Periaman, Michael P. Skinner -
Patent number: 9601468Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.Type: GrantFiled: May 4, 2016Date of Patent: March 21, 2017Assignee: Intel CorporationInventors: Michael P. Skinner, Teodora Ossiander, Sven Albers, Georg Seidemann
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INTEGRATED CIRCUIT PACKAGING TECHNIQUES AND CONFIGURATIONS FOR SMALL FORM-FACTOR OR WEARABLE DEVICES
Publication number: 20160343686Abstract: Embodiments of the present disclosure are directed toward integrated circuit (IC) packaging techniques and configurations for small form-factor or wearable devices. In one embodiment, an apparatus may include a substrate having a first side and a second side disposed opposite to the first side and a sidewall disposed between the first side and the second side, the sidewall defining a perimeter of the substrate, and a plurality of through-substrate vias (TSVs) disposed between the first side and the second side of the substrate, and a first dielectric layer disposed on the first side and including electrical routing features to route electrical signals of one or more dies in a plane of the first dielectric layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: November 12, 2014Publication date: November 24, 2016Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Kooi Chi Ooi, Shanggar Periaman, Michael P. Skinner -
Publication number: 20160324487Abstract: Embodiments described herein may fully integrate personal computing and health care into a wearable waistband having a length sensor, a pressure sensor, and a motion sensor; or into a wearable “mesh” having an array of sound sensors, which will create convenient and seamless access to a personal computer and biofeedback of the wearer. Such biofeedback from the waistband may include determining respiration rate, waist length, food quantity of a meal, sitting or sleep time, and frequency of visits to the bathroom. Such biofeedback from the mesh or array may include determining whether there is or has been damage or other issues of the heart, lungs, bones, joints, jaw, throat, arteries, digestive tract, and the like. Such biofeedback may also detect whether whether a person has an allergic reaction at a location, is drinking (and what volume of fluid), is walking, is jogging or is running.Type: ApplicationFiled: November 27, 2014Publication date: November 10, 2016Inventors: Mao GUO, Junfeng ZHAO, Michael P. SKINNER, Ke XIAO, Jiamiao TANG, Bin LIU, Li DENG
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Publication number: 20160327977Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package. In embodiments, an integrated circuit (IC) package may include a flexible substrate. The flexible substrate may have a plurality of dies coupled therewith. The IC package may include a first encapsulation material, having a first rigidity, disposed on the flexible substrate to at least partially encapsulate each die of the plurality dies. The IC package may further include a second encapsulation material, having a second rigidity, disposed on the flexible substrate. In embodiments, the second rigidity and the first rigidity are different from one another. Other embodiments may be described and/or claimed.Type: ApplicationFiled: November 12, 2014Publication date: November 10, 2016Inventors: Jiamiao Tang, Junfeng Zhao, Michael P. Skinner, Yong She, Jiun Hann Sir, Bok Eng Cheah, Shanggar Periaman, Kooi Chi Ooi, Yen Hsiang Chew
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Publication number: 20160247785Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.Type: ApplicationFiled: May 4, 2016Publication date: August 25, 2016Inventors: Michael P. Skinner, Teodora Ossiander, Sven Albers, Georg Seidemann
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Patent number: 9343389Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.Type: GrantFiled: August 14, 2015Date of Patent: May 17, 2016Assignee: Intel CorporationInventors: Michael P. Skinner, Teodora Ossiander, Sven Albers, Georg Seidemann
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Publication number: 20150357311Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.Type: ApplicationFiled: August 14, 2015Publication date: December 10, 2015Inventors: Michael P. Skinner, Teodora Ossiander, Sven Albers, Georg Seidemann
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Patent number: 9142475Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.Type: GrantFiled: August 13, 2013Date of Patent: September 22, 2015Assignee: Intel CorporationInventors: Michael P. Skinner, Teodora Ossiander, Sven Albers, Georg Seidemann
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Publication number: 20150235920Abstract: Embodiments of flow diversion devices (FDDs) are disclosed herein. An FDD may include a body formed of a body material and a plurality of thermally deformable fins arranged along the body. Individual fins of the plurality of fins may include first and second materials having different coefficients of thermal expansion (CTEs). Other embodiments may be disclosed and/or claimed.Type: ApplicationFiled: February 14, 2014Publication date: August 20, 2015Inventors: Michael P. Skinner, Sven Albers, Harald Gossner, Peter Baumgartner, Hans-Joachim Barth
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Publication number: 20150048520Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.Type: ApplicationFiled: August 13, 2013Publication date: February 19, 2015Inventors: Michael P. Skinner, Teodora Ossiander, Sven Albers, Georg Seidemann
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Patent number: 7305019Abstract: An apparatus, system, and method for an excimer laser having lasing gas and electron emitters emitting electrons upon the application of an emitting voltage is described herein.Type: GrantFiled: January 5, 2005Date of Patent: December 4, 2007Assignee: Intel CorporationInventors: Michael P. Skinner, Martha O. Neustadt
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Patent number: 6548224Abstract: A dielectric layer in a wiring substrate having a sloped sidewall. A photomask used to pattern the dielectric layer includes optical proximity features. The size and spacing of the optical proximity features are generally less than the resolution limit of the exposure tool used and do not print out on the layer. The optical proximity features provide a transition region between fully exposed material and un-exposed material, which results in a sloped sidewall of the photo-sensitive material after development. The sloped sidewall provides a more reliable thin film metal layer to contact through vias, and may be used to conserve wiring board area by allowing smaller via spacing.Type: GrantFiled: March 7, 2000Date of Patent: April 15, 2003Assignee: Kulicke & Soffa Holdings, Inc.Inventors: Ted T. Chen, Michael P. Skinner
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Patent number: 6500885Abstract: A liquid chemical formulation suitable for making a thin solid polycarbonate film contains polycarbonate material and a liquid typically capable of dissolving the polycarbonate material to a concentration of at least 1%. The polycarbonate material may consist of homopolycarbonate or/and copolycarbonate. Examples of the liquid include pyridine, a ring-substituted pyridine derivative, pyrrole, a ring-substituted pyrrole derivative, pyrrolidine, a pyrrolidine derativive, chlorobenzene, and cyclohexanone. A liquid film (36A) of the formulation is formed over a substructure (30) and processed to remove the liquid. The resultant solid polycarbonate film can later serve as a track layer through which charged particles (70) are passed to form charged-particle tracks (72). Apertures (74) are created through the track layer by a process that entails etching along the tracks. The aperture-containing polycarbonate track layer is typically used in fabricating a gated electron-emitting device.Type: GrantFiled: October 29, 1999Date of Patent: December 31, 2002Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc.Inventors: John D. Porter, Michael P. Skinner, Stephanie Simmons
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Patent number: 6323435Abstract: Low-impedance high density deposited-on-laminate (DONL) structures having reduced stress features reducing metallization present on the laminate printed circuit board. In this manner, reduced is the force per unit area exerted on the dielectric material disposed adjacent to the laminate material that is typically present during thermal cycling of the structure.Type: GrantFiled: July 29, 1999Date of Patent: November 27, 2001Assignee: Kulicke & Soffa Holdings, Inc.Inventors: Jan I. Strandberg, David J. Chazan, Michael P. Skinner
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Patent number: 6165892Abstract: A method for forming a planarized thin film dielectric film on a surface of a common circuit base upon which one or more integrated circuits are to be attached. The common circuit base includes raised features formed over its surface such that the raised features define a trench area between them. The method includes the steps of forming a first layer of the dielectric film over the common circuit base and over the raised features and the trench, then patterning the newly formed layer to remove portions of the layer formed over the raised features and expose the raised features. After the layer is patterned, formation of the dielectric film is completed by forming a second layer of the dielectric film over the patterned first layer.Type: GrantFiled: July 31, 1998Date of Patent: December 26, 2000Assignee: Kulicke & Soffa Holdings, Inc.Inventors: David J. Chazan, Ted T. Chen, Todd S. Kaplan, James L. Lykins, Michael P. Skinner, Jan I. Strandberg