Abstract: This invention relates to chemical polymer compositions, methods of synthesis, and fabrication methods for devices regarding polymers capable of displaying shape memory behavior (SMPs) and which can first be polymerized to a linear or branched polymeric structure, having thermoplastic properties, subsequently processed into a device through processes typical of polymer melts, solutions, and dispersions and then crossed linked to a shape memory thermoset polymer retaining the processed shape.

Abstract: A fixation component includes tines extending from a base portion of the fixation component. Each tine is elastically deformable between a pre-set position and an open position. Each tine includes a hook segment extending from a proximal end near the base portion to a distal end. Each tine also includes a distal segment extending from the distal end of the hook segment to a tissue-piercing tip. When positioned in the pre-set position, the hook segment extends along a pre-set curvature that encloses an angle between 135 degrees and 270 degrees, and the distal segment extends away from a longitudinal axis of the fixation component.

Abstract: A configuration of a direct drive lawnmower spindle assembly to protect sensitive electric motor components is provided. A spindle shaft of the spindle assembly is supported by upper and lower bearings. An upper end of the spindle shaft is mounted to a rotor of the electric motor and a lower end of the spindle shaft extends through the clearance opening. The lower bearing is supported by a lower bearing carrier that is mounted to the bottom of the spindle housing. The lower bearing can be serviced by removing the lower bearing carrier. A clearance gap between the spindle shaft and the clearance opening is sufficiently small to limit spindle shaft tipping to a degree that will not damage the motor. The invention also provides a friction coupling system for coupling a blade with the rotating spindle shaft.

Abstract: Tracking repeated reads to guide dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes processing elements (PEs) and a central ordering point circuit (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation. The COP's selection is based on protocol preference indicators generated by the PEs using repeat-read indicators that each PE maintains to track whether a coherence granule was repeatedly read by the PE (e.g., as a result of polling reads, or as a result of re-reading the coherence granule after it was evicted from a cache due to an invalidating snoop). After selecting the cache coherence protocol, the COP sends a response message to the PEs indicating the selected cache coherence protocol.

Abstract: Maintaining domain coherence states including Domain State No-Owned (DSN) in processor-based devices is disclosed. In this regard, a processor-based device provides multiple processing elements (PEs) organized into multiple domains, each containing one or more PEs and a local ordering point circuit (LOP). The processor-based device supports domain coherence states for coherence granules cached by the PEs within a given domain. The domain coherence states include a DSN domain coherence state, which indicates that a coherence granule is not cached within a shared modified state within any domain. In some embodiments, upon receiving a request for a read access to a coherence granule, a system ordering point circuit (SOP) determines that the coherence granule is cached in the DSN domain coherence state within a domain of the plurality of domains, and can safely read the coherence granule from the system memory to satisfy the read access if necessary.

Abstract: Maintaining domain coherence states including Domain State No-Owned (DSN) in processor-based devices is disclosed. In this regard, a processor-based device provides multiple processing elements (PEs) organized into multiple domains, each containing one or more PEs and a local ordering point circuit (LOP). The processor-based device supports domain coherence states for coherence granules cached by the PEs within a given domain. The domain coherence states include a DSN domain coherence state, which indicates that a coherence granule is not cached within a shared modified state within any domain. In some embodiments, upon receiving a request for a read access to a coherence granule, a system ordering point circuit (SOP) determines that the coherence granule is cached in the DSN domain coherence state within a domain of the plurality of domains, and can safely read the coherence granule from the system memory to satisfy the read access if necessary.

Abstract: Tracking repeated reads to guide dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes processing elements (PEs) and a central ordering point circuit (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation. The COP's selection is based on protocol preference indicators generated by the PEs using repeat-read indicators that each PE maintains to track whether a coherence granule was repeatedly read by the PE (e.g., as a result of polling reads, or as a result of re-reading the coherence granule after it was evicted from a cache due to an invalidating snoop). After selecting the cache coherence protocol, the COP sends a response message to the PEs indicating the selected cache coherence protocol.

Abstract: Providing dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes a master PE and at least one snooper PE, as well as a central ordering point (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation by the master PE. The selection is made by the COP based on one or more protocol preference indicators that may be generated and provided by one or more of the master PE, the at least one snooper PE, and the COP itself. After selecting the cache coherence protocol to use, the COP sends a response message to each of the master PE and the at least one snooper PE indicating the selected cache coherence protocol.

Abstract: Enabling atomic memory accesses across coherence granule boundaries in processor-based devices is disclosed. In this regard, a processor-based device includes multiple processing elements (PEs), and further includes a special-purpose central ordering point (SPCOP) configured to distribute coherence granule (“cogran”) pair atomic access (CPAA) tokens. To perform an atomic memory access on a pair of coherence granules, a PE must hold a CPAA token for an address block containing one of the pair of coherence granules before the PE can obtain each of the pair of coherence granules in an exclusive state. Because a CPAA token must be acquired before obtaining exclusive access to at least one of the pair of coherence granules, and because the SPCOP is configured to allow only one CPAA token to be active for a given address block, deadlocks and livelocks between PEs seeking to access the same coherence granules can be avoided.

Abstract: Providing dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes a master PE and at least one snooper PE, as well as a central ordering point (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation by the master PE. The selection is made by the COP based on one or more protocol preference indicators that may be generated and provided by one or more of the master PE, the at least one snooper PE, and the COP itself. After selecting the cache coherence protocol to use, the COP sends a response message to each of the master PE and the at least one snooper PE indicating the selected cache coherence protocol.

Abstract: Enabling atomic memory accesses across coherence granule boundaries in processor-based devices is disclosed. In this regard, a processor-based device includes multiple processing elements (PEs), and further includes a special-purpose central ordering point (SPCOP) configured to distribute coherence granule (“cogran”) pair atomic access (CPAA) tokens. To perform an atomic memory access on a pair of coherence granules, a PE must hold a CPAA token for an address block containing one of the pair of coherence granules before the PE can obtain each of the pair of coherence granules in an exclusive state. Because a CPAA token must be acquired before obtaining exclusive access to at least one of the pair of coherence granules, and because the SPCOP is configured to allow only one CPAA token to be active for a given address block, deadlocks and livelocks between PEs seeking to access the same coherence granules can be avoided.

Abstract: Nylon carpet or textile yarn may be produced at an increased rate of throughput/spinneret hole by incorporating into nylon 6.6 polymer a secondary component which improves processability and lustre by suppressing spherulitic growth. The secondary component may be a co-monomer (e.g. hexamethylene diamine/isophthalic acid) which is incorporated during polymerisation to form a random co-polymer, a polymer (e.g. nylon 6) which is molecularly dispersed in the nylon 6.6 polymer without significant copolymerisation occurring or a metal salt (e.g. lithium chloride).