Patents by Inventor Michael Patrick Chudzik
Michael Patrick Chudzik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8227874Abstract: A semiconductor structure. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.Type: GrantFiled: August 24, 2010Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: James William Adkisson, Michael Patrick Chudzik, Jeffrey Peter Gambino, Hongwen Yan
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Patent number: 8012863Abstract: A transistor with a gate stack having a metal electrode and a method for forming the same. The method includes providing a structure which includes (a) a substrate, (b) a gate dielectric layer on the substrate, and (c) a gate layer on the gate dielectric layer. The gate layer includes an oxidized layer. The oxidized layer comprises an oxidized material. Then, the structure is exposed to a first plasma resulting in removal of oxygen atoms from molecules of the oxidized material.Type: GrantFiled: January 6, 2006Date of Patent: September 6, 2011Assignee: International Business Machines CorporationInventors: Michael Patrick Chudzik, Paul Daniel Kirsch
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Publication number: 20100314697Abstract: A semiconductor structure. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.Type: ApplicationFiled: August 24, 2010Publication date: December 16, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James William Adkisson, Michael Patrick Chudzik, Jeffrey Peter Gambino, Hongwen Yan
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Patent number: 7790559Abstract: A semiconductor structure and a method for forming the same. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.Type: GrantFiled: February 27, 2008Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: James William Adkisson, Michael Patrick Chudzik, Jeffrey Peter Gambino, Hongwen Yan
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Publication number: 20090212376Abstract: A semiconductor structure and a method for forming the same. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.Type: ApplicationFiled: February 27, 2008Publication date: August 27, 2009Inventors: James William Adkisson, Michael Patrick Chudzik, Jeffrey Peter Gambino, Hongwen Yan
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Patent number: 7160771Abstract: Gate oxides having different thicknesses are formed on a semiconductor substrate by forming a first gate oxide on the top surface of the substrate, forming a sacrificial hard mask over a selected area of the first gate oxide; and then forming a second gate oxide. A first poly layer may be formed on the first gate oxide, under the hard mask. After the hard mask is removed, a second poly layer may be formed over the second gate oxide and over the first poly layer. This enables the use of high-k dielectric materials, and the first gate oxide can be thinner than the second gate oxide.Type: GrantFiled: November 28, 2003Date of Patent: January 9, 2007Assignee: International Business Machines CorporationInventors: Anthony I-Chih Chou, Michael Patrick Chudzik, Toshiharu Furukawa, Oleg Gluschenkov, Paul Daniel Kirsch, Byoung Hun Lee, Katsunori Onishi, Heemyoung Park, Kristen Colleen Scheer, Akihisa Sekiguchi
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Patent number: 7030481Abstract: A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.Type: GrantFiled: December 9, 2002Date of Patent: April 18, 2006Assignee: Internation Business Machines CorporationInventors: Michael Patrick Chudzik, Robert H. Dennard, Rama Divakaruni, Bruce Kenneth Furman, Rajarao Jammy, Chandrasekhar Narayan, Sampath Purushothaman, Joseph F. Shepard, Jr., Anna Wanda Topol
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Patent number: 6962872Abstract: A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.Type: GrantFiled: August 31, 2004Date of Patent: November 8, 2005Assignee: International Business Machines CorporationInventors: Michael Patrick Chudzik, Robert H. Dennard, Rama Divakaruni, Bruce Kenneth Furman, Rajarao Jammy, Chandrasekhar Narayan, Sampath Purushothaman, Joseph F. Shepard, Jr., Anna Wanda Topol
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Patent number: 6905944Abstract: A method for fabricating a deep trench etched into a semiconductor substrate is provided by the present invention. The trench is divided into an upper portion and a lower portion and the method allows for the lower portion to be processed differently from the upper portion. After the trench is etched into the semiconductor substrate, a nitride layer is formed over a sidewall of the trench. A layer of oxide is then formed over the nitride layer. A filler material is then deposited and recessed to cover the oxide layer in the lower portion of the trench, followed by the removal of the oxide layer from the upper portion of the trench above the filler material. Once the oxide layer is removed from the upper portion of the trench, the filler material can also be removed, while allowing the oxide layer and the nitride layer to remain in the lower portion of the trench. Silicon is selectively deposited on the exposed nitride layer in the upper portion of the trench.Type: GrantFiled: May 8, 2003Date of Patent: June 14, 2005Assignees: International Business Machines Corporation, Infineon Technologies AGInventors: Michael Patrick Chudzik, Irene McStay, Helmut Horst Tews, Porshia Shane Wrschka
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Publication number: 20040224478Abstract: A method for fabricating a deep trench etched into a semiconductor substrate is provided by the present invention. The trench is divided into an upper portion and a lower portion and the method allows for the lower portion to be processed differently from the upper portion. After the trench is etched into the semiconductor substrate, a nitride layer is formed over a sidewall of the trench. A layer of oxide is then formed over the nitride layer. A filler material is then deposited and recessed to cover the oxide layer in the lower portion of the trench, followed by the removal of the oxide layer from the upper portion of the trench above the filler material. Once the oxide layer is removed from the upper portion of the trench, the filler material can also be removed, while allowing the oxide layer and the nitride layer to remain in the lower portion of the trench. Silicon is selectively deposited on the exposed nitride layer in the upper portion of the trench.Type: ApplicationFiled: May 8, 2003Publication date: November 11, 2004Applicants: International Business Machines Corporation, Infineon Technologies North America CorpInventors: Michael Patrick Chudzik, Irene McStay, Helmut Horst Tews, Porshia Shane Wrschka
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Publication number: 20040108587Abstract: A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.Type: ApplicationFiled: December 9, 2002Publication date: June 10, 2004Inventors: Michael Patrick Chudzik, Robert H. Dennard, Rama Divakaruni, Bruce Kenneth Furman, Rajarao Jammy, Chandrasekhar Narayan, Sampath Purushothaman, Joseph F. Shepard, Anna Wanda Topol
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Patent number: 6664161Abstract: The present invention is a method and structure for fabricating a trench capacitor within a semiconductor substrate having a buried plate electrode formed of metal silicide. A collar is formed in a trench etched into a substrate; a conformal metal film is deposited thereover, and is annealed to form a silicide that is self-aligned to the collar. Silicide will not be formed on the collar, pads and other areas where the silicon is not directly exposed and hence the metal layer can be removed from these areas by selective etching.Type: GrantFiled: May 1, 2002Date of Patent: December 16, 2003Assignee: International Business Machines CorporationInventors: Michael Patrick Chudzik, Jack Allan Mandelman, Carl John Radens, Rajarao Jammy, Kenneth T. Settlemyer, Jr., Padraic C. Shafer, Joseph F. Shepard, Jr.
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Publication number: 20030207532Abstract: The present invention is a method and structure for fabricating a trench capacitor within a semiconductor substrate having a buried plate electrode formed of metal silicide. A collar is formed in a trench etched into a substrate; a conformal metal film is deposited thereover, and is annealed to form a silicide that is self-aligned to the collar. Silicide will not be formed on the collar, pads and other areas where the silicon is not directly exposed and hence the metal layer can be removed from these areas by selective etching.Type: ApplicationFiled: May 1, 2002Publication date: November 6, 2003Applicant: International Business Machines CorporationInventors: Michael Patrick Chudzik, Jack Allan Mandelman, Carl John Radens, Rajarao Jammy, Kenneth T. Settlemyer, Padraic C. Shafer, Joseph F. Shepard
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Patent number: 6579759Abstract: In a vertical-transistor DRAM cell, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a temporary insulator layer, forming a vertical spacer on the trench walls above the temporary insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the DRAM cell.Type: GrantFiled: August 23, 2002Date of Patent: June 17, 2003Assignees: International Business Machines Corporation, Infineon Technologies AGInventors: Michael Patrick Chudzik, Jochen Beintner, Ramachandra Divakaruni, Rajarao Jammy